Enhancing simulation feasibility for multi-layer 2D MoS₂ RRAM devices: reliability performance learnings from a passive network model†

Seonjeong Lee ^a, Yifu Huang ^b, Yao-Feng Chang ^c, Seungjae Baik ^d, Jack C. Lee ^b and Minsuk Koo *^e
aSchool of Electrical and Computer Engineering, University of Seoul, Seoul 02504, South Korea
^bDepartment of Electrical and Computer Engineering, University of Texas at Austin, 10100 Burnet Road, 78758 Austin, TX, USA
^cIntel Corporation, 2501 NE Century Road, 97124 Hillsboro, OR, USA
^dSemiconductor Research and Development Center, Samsung Electronics, Hwaseong-si 18448, South Korea
^eDepartment of Computer Science and Engineering, Incheon National University, Incheon 22012, South Korea. E-mail: koo@inu.ac.kr

First published on 19th July 2024

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1. Introduction

Resistive random-access memory (RRAM) has garnered significant attention for its potential applications in artificial intelligence, machine learning, and neuromorphic computing.^1–3 Comprising a switching layer (SL) sandwiched between the bottom electrode (BE) and top electrode (TE), RRAM's functionality relies on the growth and rupture process of conductive filament (CF) dynamics within the resistive switching layer. The resistive switching mechanism within RRAM is categorized into two distinct types, determined by the composition of the resistive layer and its interplay with the electrode materials: the first, oxygen vacancy filament-based RRAM (OxRRAM), is commonly referred to as valence change memory (VCM), while the second type, conductive bridge random access memory (CBRAM), is also known as electrochemical metallization memory (ECM).^4–8 Transition metal oxides such as HfOx, AlOx, ZnOx, TiOx, WOx, NiOx, and TaOx have been extensively explored as materials for the resistive switching layer in RRAM devices, owing to their remarkable endurance capabilities.^9–17 However, traditional oxide-based RRAM architectures encounter challenges such as excessive read currents, restricted integration density, and elevated power requirements.¹⁸

Recent efforts to address these challenges have sparked significant interest in two-dimensional material-based RRAM, focusing on transition metal dichalcogenides (TMDs) and hexagonal boron nitride (h-BN).^19–21 These materials offer promising features such as low power operation, significant ON/OFF ratios, and low operating voltages.²² MoS₂, in particular, is noteworthy for its bandgap ranging from 1.27 eV in its bulk state to 1.98 eV when monolayered, a high electron affinity close to 4 eV, and a dielectric constant spanning 4 to 17.²³ However, yield and endurance, crucial for memory device functionality, pose significant challenges in the application of two-dimensional RRAM.^24–28 To overcome these constraints, the development of a sophisticated model that accurately captures the device's operational mechanics is essential.

While previous studies have employed various approaches, including kinetic Monte Carlo (KMC) simulations, to understand the mechanism of oxide-based RRAM devices,^29–32 simulation studies on two-dimensional RRAM remain limited. Although some studies have conducted simulations on MoS₂-based RRAM devices,^33,34 detailed research on the impact of various parameters during the fabrication process on yield and endurance is lacking. Our research addresses this gap by focusing on the development of a reliable passive network model (PNM) that integrates critical process parameters observed during MoS₂ fabrication. Building upon our prior investigation, which established optimal processing conditions for Au/MoS₂/Au RRAM devices by adjusting layer thickness and deposition rates of the TE,³⁵ the proposed modeling approach effectively simulates the current–voltage characteristics of two-dimensional RRAM, along with their yield and endurance. These simulation results are validated against experimental data from our preceding study.

2. Device and characterization

The MoS₂ films used in this work were grown on sapphire substrates by a one-step sulfurization process at the temperature of 550 °C.³⁶ A water-assisted transfer technique was used to transfer the grown MoS₂ film onto the targeted SiO₂/Si substrates with Au bottom electrodes patterned by e-beam lithography and deposited by e-beam evaporation. Top electrodes were patterned and deposited consequently under the same process as the bottom electrodes. Different evaporation energies are intentionally applied on different batches of samples (Fig. S1, ESI†). Higher evaporation energy leads to higher deposition rate and kinetic energy of Au atoms, which would introduce more defects on the MoS₂ films.³⁵ By varying the defect numbers on MoS₂ films, the resistive switching mechanisms can be revealed by studying the yield and endurance performance of the devices. The fabricated devices were measured on a Cascade probe station with an Agilent 4156 semiconductor analyzer under ambient conditions. Data collected from the devices were used in the construction of the model in this work.

3. Modeling and validation

3.1 Passive network model

The experimental results discussed in the preceding section indicate that various fabrication parameters, such as the thickness of MoS₂ material and the deposition rate of TE, can significantly impact the yield and endurance of the device. In this study, we propose the PNM that differs from conventional simulation methods by not requiring complex additional parameters to understand these experimental results. Fig. 1a shows a resistive circuit model composed of numerous resistors arranged vertically, horizontally, and diagonally in the MoS₂ resistive switching layer. This PNM is divided into two regions based on the degree of damage in the resistive switching layer: a ‘damaged layer’ and a ‘switching layer’ (Fig. 1b). The ‘damaged layer’ of the MoS₂ film, exposed during the e-beam deposition process, is defined as a permanently formed amorphous layer due to irreversible damage from high-energy Au atoms.^37,38 Meanwhile, the ‘switching layer’ of the MoS₂ film, which remains relatively undamaged in the same process, serves as the principal switching layer (Fig. 1c).

According to prior studies,^33,39 the damaged layer formed during the cleaning and TE deposition processes exerts a direct influence on the formation of conductive pathways within the switching layer, akin to the conductive filaments observed in oxide-based devices. Notably, unlike conductive filaments that physically connect the top and bottom electrodes in oxide-based devices, virtual conductive filaments can form within the ultrathin layers of MoS₂ material. When multiple virtual conductive filaments are formed, the path for current flow increases, thus elevating the resistance ratio between the high resistance state (HRS) and the low resistance state (LRS). The principles of this mechanism have been supported by STM (scanning tunnelling microscopy) images in previous research.^22,40 The referenced study utilized a gold STM tip and I–V characterization results to perform an analysis simulating the functioning of memory devices in MoS₂/Au thin films. The STM images show the initial state of sulfur vacancies before voltage is applied and the altered state after SET and RESET, as well as the sulfur vacancies being substituted by Au atom/ion during the SET process. These images, along with the corresponding I–V measurement data, provide concrete experimental evidence that the resistive switching phenomenon is caused by the migration of metal atoms/ions from the electrode to the vacancies. Thus, sulfur vacancies play a crucial role in the resistive switching characteristics of memristor devices. Remarkably, through TEM image analysis, we observed the formation of numerous defects, such as sulfur vacancies, which occurred depending on the TE deposition rate. These defects, much like sulfur vacancies, were measured to conduct excessive current, indicating they can be regarded as being in the LRS.^41,42

In this study, we analyzed the possibility of initial failure by classifying devices that either did not undergo the SET process or remained in the LRS during the initial I–V measurements as invalid. Among these, cases in the LRS due to initial excessive current accounted for about 84% of the total, confirming this as a major cause of yield and endurance degradation. To address this issue, we investigated the changes in yield and endurance at the same TE deposition rate while increasing the thickness of MoS₂ from monolayer (T1) to tri-layer (T3),³⁵ and we observed the possibility of performance improvement with increased thickness in this process. Based on experimental results, a resistance model according to the atomic model was set up and applied to the simulation. The atomic model of monolayer MoS₂ is presented in Fig. 2a, while atomic models of various thicknesses under the same defect probability are shown in Fig. 2b and c.

To convert the atomic structure into a resistance model, we modeled the switching layer and damaged layer as high resistance unit (HRU) and low resistance unit (LRU). The corresponding resistance circuit is shown in Fig. 2d, modeling the areas with and without defects as LRU and HRU, respectively, based on the relationship between the TE deposition rate and defect density. Furthermore, our simulation incorporated parameters related to defect distribution and thickness (T1, T2, and T3) to evaluate their effects on the yield and endurance of the Au/MoS₂/Au device fabrication process. Fig. 2e and f visually present resistance networks of different thicknesses under the same defect probability. Using this model, the simulation was able to ascertain the impacts of defect distribution and thickness on the yield and endurance. The detailed aspects of this model and its simulation method are described in the following section.

3.2 Modeling methodology

The PNM simulation was developed to reproduce the switching behavior of MoS₂ based RRAM devices, and the workflow is visually depicted in Fig. 3a. In the PNM framework, each resistor is assigned one of two possible states: the HRU indicating high resistance ‘off state’, or the LRU indicating low resistance ‘on-state’. Initially, the majority of resistors are set to the HRU state to represent a pristine state. When a voltage is applied between the TE and BE, the voltage at every node in the PNM is calculated using Kirchhoff's laws, and the state of each resistor is determined by the voltage difference across it, Δv (Fig. S2, ESI†). During the SET process, a resistor unit switches from HRU to LRU only when Δv exceeds the predefined threshold voltage v_off. Conversely, during the RESET process, it reverts from LRU to HRU only if Δv reaches below the onset voltage v_on.

• For the SET process:

HRU → LRU when voff < Δv	(1)

• For the RESET process:

LRU → HRU when von < Δv.	(2)

where v_off and v_on represent threshold voltages that are distinct from V_set and V_reset as identified in the I–V curve for the SET and RESET processes, respectively. These threshold voltages indicate the specific values at which each individual resistor switches state.

The operational principle of this model was proposed in the previous studies to mimic the unipolar resistive switching characteristics of oxide-based RRAMs.⁴³ Unlike the research that emulated TiO₂-based RRAM mechanisms through vertical and horizontal resistances, our study applies the dissociation–diffusion–adsorption (DDA) model for simulating the MoS₂-based RRAM mechanism.²² The DDA model elucidates the filament growth from conductive points, and our PNM simulation incorporates this mechanism by initially placing LRU at the top and bottom of the resistance circuit progressively, and assuming that new LRU forms from adjacent LRUs during the SET process.

HRS and LRS in the PNM simulation are described using the Schottky emission model and ohmic behavior,^44,45 respectively:

• The resistance of LRS is regulated by metallic Ohmic conduction, as demonstrated in function (3). Here, the parameter A₁ indicates the current, and B₁ is influenced by the intrinsic resistance of the measurement devices.

LRS = A1V + B1	(3)

• The resistance of HRS is controlled by the Schottky emission model. Here, the parameter A₂, B₂ and C₂ in function (5) is defined by the maximum voltage (V_max) in the RESET process. As the V_max increases during the reset process, the resistance states change continuously.

	(4)

	(5)

Where V, J, A*, T, q, ϕ_B, E, ε₀, ε_r represent the voltage, current density, Richardson constant, absolute temperature, elementary charge, Schottky barrier height, Boltzmann's constant, electric field across the dielectric, permittivity of free space, and relative permittivity, respectively. Using these parameters, HRS and LRS were set based on the Schottky emission model and ohmic behavior, reflecting the DC experimental data. The conduction mechanism-based parameters and their values are detailed in Table S1 of the ESI.†

Based on this algorithm, the simulations for yield and endurance were conducted in accordance with the workflow chart shown in Fig. 3b and c. In the initial phase, resistance values were set in consideration of defect distribution, while the total number of operations N_total and the number of successful switching operations N_sucess were inputted as parameters. For the yield simulation, the SET process was repeated for the predefined total number of operations N_total, and the ratio of successful to total operations (N_sucess/N_total) was measured. Similarly, the endurance simulation repeated the SET and RESET processes for N_total cycles, terminating the simulation if the resistance ratio between HRS and LRS under a 0.3 V read voltage was less than 10 for three consecutive times. It measures the number of successful operations N_sucess.

To verify the operation of the resistance switching algorithm through PNM simulation, we utilized an 80 × 80 resistor matrix to visually observe the virtual filament formation process (Fig. 4). As voltage was applied through resistors with defects, HRUs were converted to LRUs, confirming the growth of filaments from the TE to the BE. Additionally, by adjusting the initial probability of defects at the top/bottom from 30%/1% to 50%/3% and conducting simulations, we observed the formation of multiple virtual filament paths at the bottom of the simulation region. With a defect occurrence probability of 30%/1% (Fig. 4a), filaments gradually grew from the TE to the BE along with the applied voltage. Even at a higher defect occurrence probability of 40%/2% (Fig. 4b), despite the low voltage applied, we observed the formation of multiple filament paths by LRUs. However, at the highest defect occurrence probability of 50%/3% (Fig. 4c), numerous conductive points influenced the number of filaments, leading to initial failure phenomena. These observations are consistent with experimental results of yield reduction due to increased TE deposition rates and the filament formation paths shown through the penetration model align with previous research.³³ These results clearly illustrate the impact of variations in defect density on filament formation and, by aligning with measured outcomes, effectively validate the PNM.

3.3 Model validation and discussion

Upon applying voltage between the TE and BE, Kirchhoff's laws were utilized to calculate the voltage at every node within the PNM, thereby determining the corresponding current for the RRAM device. Consequently, we are able to derive the I–V curve from the simulation. By adjusting the PNM matrix size and defect probability, we identified conditions that produce I–V curves similar to those measured in previously fabricated Au/MoS₂/Au RRAM devices. Fig. 5a shows results closely matching the graph of a device fabricated under a 40 × 10 matrix condition with a 30% defect probability in the TE region and 1% in the BE region. Fig. 5b shows the distribution of V_SET and V_RESET threshold voltages over 100 repeated SET/RESET cycles. The simulation results showed V_SET occurring between 1 V and 3.5 V, and V_RESET between −0.2 V and −1 V, distributions that matched the outcomes of the fabricated devices.

To further explore the relationship between defect probability and yield in PNM simulations, yield simulations were performed at various defect probabilities. Fig. 6a illustrates the methodology for identifying defect probabilities that align with the characteristics of previously manufactured Au/MoS₂/Au RRAM devices. The yield simulations for all tested defect probabilities revealed defect ratios corresponding to low, medium, and high Au deposition rates as 30%/1%, 40%/2%, and 50%/3%, respectively. Fig. 6b and c show the trends in yield and endurance against device thickness for three specific defect probabilities (low, medium, and high). Conditions with high defect ratios exhibited a significant decline in yield and endurance when compared to conditions with low defect ratios. This diminishing trend was somewhat alleviated with an increase in device thickness, which in turn enhanced yield and endurance. These simulation results are consistent with empirical data from fabricated Au/MoS₂/Au RRAM devices, demonstrating that at lower TE deposition rates, the diffusion of Au ions/atoms has a lesser impact on the switching layer, thereby improving yield and endurance. The yield simulations verified that low defect ratios mitigate the risk of initial failure phenomena, while endurance simulations indicated that preventing the accumulation of LRU in the switching layer results in better resistance to electrical stress.^46,47 Moreover, across all defect ratios, thinner layers of MoS₂ were more susceptible to Au diffusion towards the BE. In contrast, thicker layers of MoS₂ diminished the likelihood of forming multiple filaments, thereby positively influencing yield and endurance.

Note that the resistance images under low defect probability conditions for different thicknesses (T1, T2, T3) have been studied in this work (shown in Fig. S3, ESI†). In the proposed model, even with the same LRU ratio, the LRU gradually decreases from TE to BE as the thickness increases, resulting in a longer switching layer when a virtual filament is formed. The thickest MoS₂ layer (T3) includes more resistance, contributing to filament formation and reducing reset failures. In contrast, the thinnest condition (T1) relies on a few individual resistances to change states, which may not reset in the next cycle, leading to reset failures and reduced endurance performance. These results show that the simulation and experimental results are consistent, thereby verifying the accuracy of the model.

We extended the application of our PNM beyond our own fabricated Au/MoS₂/Au RRAM devices to include MoS₂-based RRAM devices previously investigated by Wu et al. facilitating a comparative analysis.³⁹Fig. 6d shows the yield results from PNM simulations in comparison with those of Wu's group's MoS₂-based RRAM devices. While our Au/MoS₂/Au RRAM devices vary in defect probability with TE deposition rate, Wu's group's devices vary with radiation exposure after MoS₂ deposition. To analyze the correlation between Wu's group's MoS₂-based RRAM devices and simulation outcomes, we fixed the BE defect probability and conducted 10000 simulations for five different TE defect probabilities. The simulated yields, indicated by error bars, closely follow the trend of the fabricated devices’ yields. A lower defect count promotes filament formation, enhancing yield, while a higher defect count leads to an upsurge in current flow, diminishing yield. Notably, the yield does not continue to increase as the top defect probability decreases. This phenomenon occurs because when MoS₂ with good crystallinity and few defects is applied to the device, the number of conductive points available for filament formation decreases, preventing the initial SET from occurring. This observation aligns with the experimental results (Fig. S4, ESI†).

In this study, we introduced the PNM, a distinct approach from traditional KMC simulations. This model possesses the significant advantage of allowing a more detailed analysis of the metal ion penetration process without the need for intricate parameter adjustments. The simulation results confirmed consistency with the data of research on actual fabricated MoS₂-based RRAM devices. Particularly, the PNM facilitated understanding the process of virtual filament formation and effectively predicted and analyzed the impact of various variables, such as TE deposition rate and thickness conditions for the fabrication process, on the device's yield and endurance, in alignment with actual measurement results.

4. Conclusions

In this study, we proposed a modeling tool designed to simulate the resistive switching behavior of 2D RRAM devices. This tool offers the advantage of evaluating the yield and endurance performance of MoS₂-based RRAM devices simply through I–V simulations.

Previous studies have primarily focused on simulating only the endurance of MoS₂-based RRAM devices, without adequately considering the defects occurring during the fabrication process.^33,34 To overcome this limitation, this study developed a new modeling approach that concurrently assesses yield and endurance based on I–V characteristics. Particularly, by introducing defect distribution and layer thickness as key variables during the TE deposition process, we improved upon existing modeling tools that require complex parameters.

Using the developed model, we conducted yield and endurance simulations of MoS₂-based RRAM devices. The simulated outcomes are well matched with characteristics of actual devices, enabling validation of our model. In our study, Au/MoS₂/Au devices demonstrated that an increase in defects leads to a decrease in both yield and endurance, evidenced by initial failures. Additionally, by applying our model to MoS₂-based RRAM devices fabricated by other groups, we replicated the trend where fewer defects correlate with diminished yield and endurance. The simulations suggest that minimal defects hinder filament formation, thereby affecting device performance. These findings confirm our model's capability to accurately reproduce results from measured devices.

While our model conducted I–V simulations based on Schottky emission, it did not fully consider various non-linear conduction characteristics, particularly space charge limited conduction. This limitation represents an opportunity to enhance the model's comprehensiveness and applicability in future research and design initiatives. By incorporating a broader range of conduction mechanisms, the expanded model will not only deepen our understanding of the underlying physical processes but also improve predictive accuracy, especially in devices where these complex interactions significantly impact performance.

Furthermore, exploring these conduction characteristics could facilitate the design of more efficient electronic components by pinpointing key factors that limit device performance under diverse operating conditions. Our future work aims to make a substantial contribution to the optimization of semiconductor devices, potentially benefiting applications in neuromorphic computing systems.

Data availability

Data supporting this study are included within the article and ESI.† The input parameters of the model supporting this study are available from the repository “Passive-Network-Model” at https://zenodo.org/doi/10.5281/zenodo.12652558. Access to the modeling data is subject to approval and a data sharing agreement due to the requirement of Incheon National University. The experimental data supporting this study are available on reasonable request.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by Incheon National University Research Grant in 2024.

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d4cp02669a

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