Yuwen
Cai
ab,
Wei
Yu
ab,
Qiuhao
Zhu
ab,
Xiyuan
Liu
ab,
Xiao
Guo
a and
Wenjie
Liang
*abc
aBeijing National Center for Condensed Matter Physics, Beijing Key Laboratory for Nanomaterials and Nanodevices, Institute of Physics, Chinese Academy of Sciences (CAS), Beijing 100190, China. E-mail: wjliang@iphy.ac.cn
bSchool of Physical Sciences, University of Chinese Academy of Sciences, Beijing 100190, China
cSongshan Lake Materials Laboratory, Dongguan, Guangdong, China
First published on 29th May 2025
The development of memristors presents a transformative opportunity to revolutionize electronic devices and computing systems by enabling non-volatile memory and neuromorphic computing. Silicon oxide memristors are particularly promising due to their potential for low cost, high integration and compatibility with existing manufacturing processes. In this study, we statistically investigate the switching mechanisms of a nanoscale (sub-2 nm) silicon oxide memristor at different temperatures. As a unipolar memristor, the average set voltage (switching from a high resistive state to a low resistive state) rises with a temperature drop, while the average reset voltage (switching from a low restive state to a high state) drops slightly with the temperature drop. Standard deviation of these values increases as temperature decreases. These behaviors are analyzed based on the Weibull distribution. Statistical results suggest that the set process involves the formation of Si conducting filaments promoted by the diffusion of oxygen ions from oxygen vacancies, while the reset process involves Joule heat-driven conductive filament rupture and silicon–oxygen recombination, requiring intensified heating at higher environmental temperatures to counteract extended oxygen ion migration. Beyond general resistive switching mechanisms involving only the formation and rupture of Si conductive filaments, our insights provide a novel understanding of the stochastic mechanisms of the switching process at the atomic level, with significant implications for future neuromorphic computing applications.
The switching mechanisms in silicon oxide RRAM devices have been broadly classified into intrinsic resistive switching (RS) of the oxide and extrinsic switching involving diffusive metal electrodes. Intrinsic switching is particularly promising because it avoids the potential instability in CMOS circuits caused by electrode ion diffusion during extrinsic switching. Transmission electron microscopy (TEM) studies have shown preliminary indications of Si nanocrystal crystallization and aggregation inside silicon oxide upon RS, suggesting that RS in intrinsic silicon oxide RRAM is primarily due to the formation and rupture of Si conductive filament (Si CF).9,17,18 However, experimental studies of the mechanisms for the formation and dissociation of Si CF are still insufficient, leaving critical factors (such as detailed switching dynamics, temperature-dependent defect migration and size effects16,19–25) affecting the switching process undefined. It is desirable to study the switching mechanisms of a pure and simple device, such as a nanoscale Si CF memristor with a single Si nanocrystal, to elucidate the intrinsic switching mechanisms.
In this article, we fabricate nanometer-sized (sub-2 nm) silicon oxide memristors in graphene–SiO2–graphene nanogaps and investigate their switching behaviors at various temperatures. The ultimate device's size benefits our study in limiting switching events within a presumably single domain (Si single nanocrystal or filament typically sized 3–5 nm (ref. 17 and 18)), ruling out the complication of multi domain switching. As expected, the set and reset voltages of our devices vary with time, which is consistent with other reported silicon oxide memristors. The statistics of these values are examined utilizing a percolation model that includes the formation and rupture of defect-related conductive cells. We found that the formation of Si CF in the set process is thermally influenced by the diffusion of oxygen ions from oxygen vacancies, and the rupture of Si CF in the reset process is primarily driven by localized Joule heating, yet elevated environmental temperatures demand increased Joule heating to overcome thermally extended oxygen ion migration distances. Additionally, we demonstrate that the high local temperatures induced by graphene nanoconstriction electromigration generate initial oxygen vacancy clusters, significantly enhancing the electroforming efficiency of our devices. This comprehensive investigation provides key insights into refining the technology and improving the performance of silicon oxide RRAM.
The cumulative probability function (CDF) of the Weibull distribution is defined as follows:
F = 1 − exp(−x/x63%)β |
Therefore, the set/reset Weibull distribution function is similarly defined by the set/reset cumulative probability: FVset/reset, as W(Vset/reset) ≡ ln(−Ln(1 − FVset/reset)) = βVset/resetln(Vset/reset/Vset/reset, 63%).
The mean value of the Weibull PDF is given by
The standard deviation is
The Weibull slope β ≫ 1 is found in our experiments. Therefore, with an increase in the Weibull slope, the mean value increases and the standard deviation decreases.
Initially, graphene nanogap devices are prepared by mechanically exfoliating a few-layer graphene onto a SiO2 substrate and patterning it into the nanoconstriction of width W = 1 μm and length L = 1 μm by electron beam lithography (EBL) and reactive ion etching (RIE) with oxygen gas. A second-step EBL is used to define electrical contacts to the graphene nanoconstriction, followed by the thermal evaporation of Cr/Au (3 nm/60 nm), as depicted in Fig. 1a. To create graphene nanogaps, we apply a feedback-controlled electromigration26 DC voltage to the device at room temperature under vacuum conditions (10−6 mbar), as shown in Fig. 1b. A sudden decrease in current at an applied voltage of 8 V is observed, which is attributed to the sublimation of carbon atoms.27–29 This phenomenon enables the device to reach a target resistance of over 1 MΩ, resulting in the controlled DC voltage dropping to zero. Thus, the formed graphene–SiO2–graphene nanogap is estimated by measuring the tunneling current at a low bias (Fig. S1†). Fitting the low bias voltage tunneling current with the Simmons model30 and atomic force microscopy (AFM) measurements revealed a sub-2 nm gap size (approximately 1.5 nm, as portrayed in Fig. S1†), providing clear evidence for the successful fabrication of graphene nanogap devices on a silicon oxide substrate.
Electroforming of SiOx memristors is performed by multiple voltage ramps to the nanogap device. An insulating behavior is initially observed, followed by current jumps at a voltage around Vform = 3.3 V (called electroforming voltage), which is attributed to the dielectric soft breakdown and the concurrent generation of oxygen defects in silicon oxide.31 As the voltage ramping continues, an oscillatory current I (V) is observed, as depicted in Fig. 1c (red curve), likely owing to the stochastic migration of defects, leading to the formation of an unstable Si CF.32–34 After over 10 cycles of voltage ramping between 0 V and 8 V, devices eventually showed a stable IV characteristic (Fig. 1c, blue curve), indicating that a stable Si CF is formed. The detailed evolution of conductance changes during voltage cycles is represented in Fig. S2a.† In contrast, no electroforming phenomenon is observed in graphene–Si3N4–graphene nanogap devices (Fig. S2b†), proving SiOx memristor rather than the motion of carbon atoms35 in the graphene nanogap.
A typical RS characteristic curve extracted from multiple cycles of our as-formed SiOx memristor is shown in Fig. 1d, similar to other SiOx memristor studies.8–10,15,36 Initially, the device maintains a low resistance state (LRS) of the Si CF until the voltage reaches approximately 6 V. At this point, a decrease in current is detected, transitioning the device into a high resistance state (HRS), marking the reset process, with the corresponding voltage identified as the reset voltage Vreset. Notably, the HRS is retained as the voltage returns to zero. Upon ramping the voltage to 3 V, a current jump occurs, indicating the set process at set voltage Vset. This unipolar RS phenomenon, where set and reset occur at the same polarity with Vset < Vreset, is highlighted in Fig. 1d and aligns with previous studies on SiOx RS.9,15,37,38 The notably high reset voltage of approximately 6 V, while eliminating the need for current compliance, poses challenges for device power consumption, reliability, and system complexity.
The stability of our SiOx memristor is evaluated through pulse cycling and retention time measurements. As illustrated in Fig. 1e, the device exhibits stable switching characteristics of over 10000 cycles under 0.1 V read voltage, with set and reset operations performed at 5 V and 10 V voltage pulses, respectively. Conductance measurements for both ON and OFF states reveal negligible degradation, confirming reliable cycle endurance. Furthermore, ON and OFF state resistances demonstrate excellent retention stability for over 105 s at a read voltage of 0.1 V, as shown in Fig. 1f, underscoring the device's exceptional non-volatile data retention capability. These results align closely with the prior stability performance of SiOx memristors,8–10,15,36 reinforcing the reliability of our study. Moreover, ON state power consumption at a read voltage of 0.1 V is comparable across devices on the order of microwatts (∼0.1 μW), while the OFF-state power consumption ranges from picowatts to nanowatts (pw–nW). The related functions of neuromorphic computing, such as multilevel and synaptic plasticity, are also demonstrated in Fig. S7 of the ESI.† These results highlight the potential of our device for applications in neuromorphic computing.
A distinctive feature of our device is that set voltage Vset = 3 V is close to the electroforming voltage Vform = 3.3 V (red L-shaped arrow in Fig. 1c), unlike other studies where Vset ≪ Vform.9,11,15,17,37–39 In these studies, much larger electroforming voltage Vform is required to create a silicon conductive path between two electrodes (>10 nm), presumedly over several oxide domains. The reset process involves breaking only a small portion of this path. Therefore, their set process merely reconnects the broken section, influenced by the shape and location of the broken section, introducing stochasticity and failing to fully capture the intrinsic characteristics of the Si CF's intrinsic characteristics. In contrast, our device forms the Si CF within a very small nanogap (<2 nm), resulting in electroforming voltage Vform closely matching the set voltage Vset. This indicates that the set process in our device directly involves the formation and complete re-formation of the Si CF rather than merely bridging a pre-existing break.9,17,18 Consequently, our devices encompass all the research conditions in unipolar SiOx memristors; investigation of our nanogap devices could provide a clear picture of the intrinsic characteristics of unipolar SiOx switching.
Switching uniformity issues of typical SiOx memristor is repeated and confirmed in our study by operating those nanoscale devices over one hundred times under constant conditions to obtain the statistics. A stochastic variation in the switching threshold voltage of one device is illustrated in Fig. 2a for operation at room temperature. Set threshold voltages group around 3.2 V with a difference between cycles as large as 0.8. A similar pattern appears for the reset process, with the threshold voltages group around 6.3 V and a variation of 2.6 V. There is no clear correlation between variations in Vset and Vreset of the same trace, indicating random variation of the set and reset voltage. To further investigate this stochastic switching process, we primarily focus on analyzing the statistical distribution of these switching threshold voltages and their temperature dependence.
A ramping voltage is applied with a fixed ramping rate of 0.4 V s−1 over 150 sweep cycles at temperatures ranging from 250 K to 350 K. The statistical distributions of the set/reset voltage at three distinct temperatures are presented in histograms, as depicted in Fig. 2b–g. A clear conclusion can be drawn that higher temperatures correspond to lower set voltage Vset (Fig. 2b–d), and an increase in reset voltage Vreset is consistent with previous studies.40 Moreover, a narrower broadening of the set/reset voltage distribution is observed at higher temperatures. Our nano memristor devices cannot be operated below 250 K, indicating that thermal activation is involved in the process (see Fig. S4 in ESI†).
To quantitatively analyze these data, the Weibull distribution is utilized, which models the evolution of defects, leading to percolation path formation, consistent with the analysis of switching dynamics in RRAM devices.41–43 Black curves illustrated in Fig. 2b–g are fittings of our data according to the Weibull distribution, which shows satisfying agreements, offering average values and standard deviation of Vset and Vreset for different experimental conditions.
Fig. 3 illustrates the extracted switching threshold voltages for the set/reset processes over a temperature range of 250 K to 350 K using the Weibull distribution model. Notably, the variability of set/reset voltages significantly increases as temperature decreases, indicating greater stochasticity in switching operations at lower temperatures, particularly near 250 K. Conversely, distinct trends are observed in the mean values of the set and reset voltages as the temperature varies. The mean set voltage decreases with increasing temperature, indicating a thermally activated process in which higher temperatures facilitate thermal activation. This thermal activation enables the transition from the HRS to the LRS more readily at elevated temperatures, leading to decreased set variability at higher temperatures. For the reset process transitioning from LRS to HRS, the formed Si CF is in a metastable state44 influenced by thermal excitation. At higher temperatures, this metastable structure becomes more stable, requiring more energy to disrupt. Consequently, the mean reset voltage increases slightly as the temperature increases, whereas its variability diminishes. This suggests that the thermal stability of the silicon conductive filament in the LRS is enhanced at elevated temperatures, reducing susceptibility to rupture by external electric fields.
![]() | ||
Fig. 3 Mean value and standard deviation of switching threshold voltages from the Weibull distribution of set/reset voltage at representative temperatures ranging from 250 K to 350 K. |
To understand temperature-related switching behavior, we model the set/reset process forming Si CF as a single path composed of N resistive switching cells, as described by the percolation model.45 In this model, Si CF, spanning the nanogap length dgap, is conceptualized as a chain with N cells of size a0, as illustrated in Fig. 4a. Each cell has a switching probability λ from a normal insulating cell to a conductive defective cell when subjected to an electric field. Because a defective cell triggers more cells to switch, switching probability λ is proportional to the ratio of defected cells in the filament.
During the set process, with an applied voltage having a ramping rate R over time t such that V(t) = Rt, the time evolution of λ follows the relationship45λ ∝ (t/τT)α, where α is the voltage-independent exponent that models the nonlinearity of the defect generation and τT is the characteristic time for defect generation. τT corresponds to the power-law rate of the voltage:46τT = τT0(V/dgap)−m, where τT0 and m are constants. We can expect the statistically Weibull function to evolve linearly with lnVset,41 with a slope βVset is given by
βVset = (m + 1)αN. | (1) |
Room temperature Weibull distribution function W(VSET) is depicted in Fig. 4b, derived from 150 ramping voltage stress sweep cycles during the set process. The linearity observed in the Weibull plot substantiates the validity of the percolation model analysis.
As previously mentioned, the set process is thermally activated and fails to set operation stably at temperatures below 240 K (Fig. S3†). Thus, the defect switching rate adheres to the Arrhenius law, modeled as ∂λ/∂t ∝ exp(−Ea1/kBT), where Ea1 is the activation energy of defect switching in a cell, kB is the Boltzmann constant and T represents the environmental temperature. Consequently, the temperature dependence of the Weibull slope can be expressed as follows (details in ESI subsection 1.4†):
![]() | (2) |
During the set process, the formation of the Si CF involves the breaking of silicon–oxygen bonds, resulting in the generation of oxygen vacancies and oxygen ions.8 The accumulation of these oxygen vacancies ultimately leads to the formation of the conductive pathway. However, for effective defect formation, it is essential not only to generate oxygen vacancies and ions but also to ensure the effective separation of oxygen ions from oxygen vacancies. The separation of oxygen vacancies and ions, facilitating the creation of effective defect cells, and the migration of oxygen ions have been substantiated.39,44 Before the set operation, the device is in HRS, and the Joule heating effect (∼nW) in HRS is negligible owing to the minimal current, ensuring that the temperature of the Si CF remains equivalent to the environmental temperature in HRS. The Arrhenius activation energy of 0.18 eV observed in this study, which matches the oxygen ion migration energy barrier, indicates that at lower temperatures, the generated oxygen ions cannot adequately separate from the oxygen vacancies to form effective defect sites. Consequently, the Si CF cannot form during the set process at low temperatures. The correspondence of the obtained activation energy with the oxygen ion migration energy barrier highlights the necessity for the effective separation of oxygen vacancies and ions for defect formation, explaining the inability of the device to undergo the set process at low temperatures and underscoring the validity of our results.
Based on our understanding of device operation, we now delve into the mechanisms driving the reset process. The silicon oxide intrinsic reset process can be influenced by several factors, including thermal effects,49 electromigration,50 and proton exchange reactions.51 In our device, the reset process is predominantly governed by thermal effects owing to unipolar resistive switching and a lack of hydrogen in the thermally oxidized silicon oxide substrate. Previous in situ TEM measurements showed non-crystallization of Si nanocrystals during the reset process.17 However, the role of oxygen migration could be overlooked. The reset process is fundamentally characterized by the rupture of the Si CF. This can be effectively described by the thermal dissolution model illustrated in Fig. 5a (inset). In this model, the rupture occurs as the conductive cells of the Si CF diffuse outward, driven by a temperature rise due to Joule heating49 as follows:
![]() | (3) |
![]() | (4) |
βVreset = γn(M + 1), | (5) |
The cumulative probability of reset voltage is measured over 150 cycles across a temperature range of 250 K–350 K. The Weibull distribution function against lnVreset at different temperatures (from 250 K to 350 K) is also plotted in Fig. 5a. A clear piecewise linear behavior with different slopes becomes apparent, indicating that the number of cells n involved in the reset process is not fixed according to eqn (5). Fig. 5b shows the Weibull distribution function of reset voltage at 255 K, accompanied by a piecewise linear fit and corresponding Weibull slopes. These slopes reflect different diffusion quantized numbers: n = 1, 2 and 10, corresponding to β0, 2.1β0 and 9.9β0, respectively, where β0 represents the Weibull slope of a unit cell with n = 1. This non-controlled n in the reset process could be why the variation in Vreset is larger than Vset, suggesting importance of further control of n to achieve uniformity of SiOx memristors. As illustrated in Fig. 5c, the piecewise Weibull slopes at temperatures from 250 K to 350 K divided by the unit cell Weibull slope (n = 1) for each temperature are plotted. These slopes converge into a single slope as the temperature rises above 330 K, indicating that diffusion is less active at higher temperatures. The piecewise linearity observed at relatively low temperatures corresponds to a greater diffusion of cells owing to the reduced stability of Si CF at these temperatures, thus making the reset process easier at lower temperatures.
Beyond the piecewise linear property, the minimum piecewise Weibull slope at each temperature, which is assumed to correspond to the unit diffusion number n = 1, is also found to be temperature dependent; it increases as the temperature increases (Fig. 5d blue dots), which is consistent with eqn (5). The fit (Fig. 5d red line) exponent for reset evolution is γ = 41 ± 8. Activation energy can be obtained from the fit parameter, with Ea2 = −37 ± 3 meV. The negative activation energy is consistent with the fact that more cells are active in the reset process and Vreset increase with temperature. In studies of the reset voltage dependence on environmental temperature in SiOx memristors, planar unipolar silicon oxide memristors,52 which are similar to our configuration but with a larger 40 nm gap size, applied Fowler–Nordheim (FN) tunneling to initiate the reset process. However, FN tunneling is temperature independent, which implies that the reset voltage is independent of temperature variations. In contrast, our observations show that reset voltage varies with temperature. Consequently, FN tunneling as the reset mechanism may not be responsible for the reset process in our devices. Observations in unipolar 60 nm SiOx memristor40 have revealed a trend consistent with our findings: the reset voltage increases as environmental temperature increases. This behavior was attributed to the growth of Si CF at higher temperatures. However, in our resistive switching measurements across different temperatures, we do not observe a significant increase in the memristor's conductance with an increase in temperature (see Fig. S6 in ESI†). Moreover, our devices, with sizes below 2 nm, rule out the mechanism of Si CF constant growth at high temperatures. In contrast, a similar trend of increasing reset voltage with increasing temperature was reported in bipolar 2 nm SiOx memristor,53 comparable in size to ours.
In such bipolar systems, this phenomenon is attributed to thermally enhanced oxygen ion diffusion distances at higher environmental temperatures, necessitating a stronger electric field to retract oxygen ions toward the Si CF during the reset process. However, our unipolar devices operate in a unipolar mode. Despite the distinct switching mechanisms between bipolar and unipolar modes, enhanced oxygen ion diffusion distances at elevated temperatures are a shared phenomenon. Consequently, we propose that the thermally extended diffusion distance of oxygen ions under elevated environmental temperatures requires amplified Joule heating to facilitate silicon atom diffusion, enabling recombination with oxygen ions and ultimately leading to the rupture of the Si CF.
This mechanism is consistent with our observations under ambient conditions. The abundance of oxygen atoms in the air causes the Si CF to combine more readily with oxygen atoms, resulting in a lower reset voltage (Fig. S4†). However, once the device transitions to an HRS, the pervasive presence of oxygen atoms in the air prevents a further set transition to an LRS. It can only transition back to the LRS by returning the device to a vacuum environment.
Thus far, we have successfully explained the switching mechanism of the silicon oxide memristor at the nanoscale. However, the sudden current increase observed during the electroforming process (Fig. 1c) deviates from the gradual increase typically observed in conventional metal–insulator–metal (MIM) structures characterized by edge defects or silicon-rich SiOx films.9,10,19 Therefore, pre-existing oxygen vacancies in our device accelerate the generation of another oxygen vacancy nearby,54 which is induced by the electromigration process of graphene nanoconstriction. In this context, the high local temperatures generated by electromigration within the graphene nanoconstriction may contribute to the formation of oxygen vacancies, thus causing a sudden increase in current during electroforming. To investigate the influence of high local temperatures on oxygen vacancy generation, similar graphene–SiO2–graphene nanogap devices were fabricated under ambient conditions and subsequently transferred into a vacuum chamber. As shown in Fig. 6a, the electroforming process is only successful in devices undergoing electromigration in a vacuum (Fig. 6b, blue curve) but not in an ambient atmosphere (Fig. 6b, red curve). This phenomenon can be attributed to the significantly higher temperatures achieved in the graphene nanogap during vacuum sublimation compared to oxidation in air (noting that graphite's sublimation temperature is approximately six times higher than its oxidation temperature).55 Therefore, a high local temperature appears to play a crucial role in facilitating the generation of oxygen vacancies, which in turn leads to an abrupt increase in the current observed during electroforming.
To estimate local temperature during the sublimation process in our device, we employed a one dimensional (1D) quasi-stable heat conduction model, as illustrated in Fig. 6a. This model assumes that the Au electrodes and the silicon wafer are held at a fixed room temperature T0 = 300 K owing to their excellent thermal conductivity. Heat transfer is primarily mediated by graphene nanoconstriction and the silicon oxide substrate. The 1D quasi-steady heat equation is thus represented as follows:
AgKgd2T/dx2 + px − gox(T − T0) = 0, | (6) |
![]() | (7) |
For our devices, the required breakdown power is in the range of 8–10 mW. The central local high temperature is estimated to be between 1500 K and 1800 K. This is consistent with previous reports,58 in which the graphene sublimation temperature is below 2500 K. To validate that high local temperatures induced by the sublimation of graphene nanoconstriction lead to the generation of oxygen vacancies, we check changes in the same silicon oxide substrate under heating conditions. The substrate is subjected to a rapid temperature annealing (RTA) process at 1000 °C in a nitrogen atmosphere for 10 s, followed by X-ray photoelectron spectroscopy (XPS) analysis. Fig. 6c illustrates the Si 2p signals of the silicon oxide substrate before and after the RTA process. The deconvolution of the Si 2p XPS peak reveals the presence of a silicon suboxide peak Si3+ and a fully oxidized peak Si4+, positioned at 102.7 eV and 103.7 eV,59 respectively, after the RTA process. The emergence of the Si3+ valence state indicates a reduction in oxygen atoms following exposure to high local temperature for a short duration, confirming the formation of oxygen vacancies.60 Therefore, the high local temperature induced by the sublimation of the graphene nanoconstriction leads to the generation of a few oxygen vacancies, which accelerates the electroforming of the Si CF.
In general, our results in this paper illustrate a quantitative experimental understanding of the switching mechanisms in silicon oxide memristors and provide important insights into reducing the stochastic nature of the switching voltage, which is crucial for developing silicon oxide memristors or neuromorphic systems.
Footnote |
† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d5nr01019e |
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