A novel high endurance HZO FeFET with monolayer graphene inserted in the gate oxide†

Liang Chen^a, Runteng Zhu^a, Xin Gao^c, Anyu Tong^a, Hailin Peng^c, Yanqing Wu^ab, Ru Huang*^ab and Kechao Tang*^ab
aSchool of Integrated Circuits, Peking University, Beijing, 100871, China. E-mail: ruhuang@pku.edu.cn; tkch@pku.edu.cn
^bBeijing Advanced Innovation Center for Integrated Circuits, Beijing 100871, China
^cCollege of Chemistry and Molecular Engineering, Peking University, Beijing, 100871, China

First published on 25th July 2025

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1. Introduction

HfO₂-based ferroelectric field-effect transistors (FeFETs) have emerged as a promising class of non-volatile memory devices, offering several significant advantages. In terms of device integration, ferroelectric HfO₂ films demonstrate excellent compatibility with complementary metal-oxide semiconductor (CMOS) processes, well-established techniques for controlling interface states, and robust scalability.^1,2 Moreover, HfO₂-based FeFETs enable three-dimensional integration, which further enhances storage density.³ Regarding device program and erase (PRG/ERS) speeds, HfO₂-based FeFETs utilize the polarization states of FE films to modulate channel conductance, effectively distinguishing between different storage states.⁴ Data erasing is achieved by an electric field-induced switching of the ferroelectric polarization, resulting in fast speeds on the order of nanoseconds.⁵ In terms of power consumption, the polarization switching of ferroelectric HfO₂ is driven by the change in the electric field, which leads to an extremely low write energy consumption.⁶ Additionally, for data retention, the large bandgap of FE HfO₂ (∼5.5 eV) ensures low leakage current.⁷ The high coercive field (E_c, 0.8–2 MV cm⁻¹) of FE HfO₂ further minimizes the impact of depolarization fields on the polarization state, allowing HfO₂-based FeFETs to maintain data retention for over 10 years.^8,9

Although HfO₂-based FeFETs offer numerous advantages, they face a significant challenge in terms of poor endurance. The limited endurance of HfO₂-based FeFETs can be attributed to charge injection effects, which gradually shrink the memory window (MW) of the device and ultimately result in endurance failure.^10,11 Therefore, suppressing the charge injection effect is of great significance for improving the performance of FeFETs. Recent efforts have concentrated on minimizing the electric field across the IL (E_IL) during PRG/ERS operations.^12,13 Currently, the main methods to reduce the E_IL include lowering the E_c of the FE layer^14,15 and increasing the dielectric constant of the IL.^16,17 However, both approaches have limitations. For the former, the E_c is influenced by complicated factors such as phase composition, phase boundaries, and defect density which are as yet unclear,^18,19 making it difficult to achieve a stable and controllable E_c. Additionally, lowering the E_c also decreases the MW of the FeFET.^20,21 For the latter, replacing the IL with a higher dielectric constant material simultaneously impacts the interface, which may lead to degradation of the device due to FE domain wall pinning, charge trap formation, and thermal instability of the interface.^22,23 Therefore, relying solely on reducing the E_IL to improve FeFET endurance still requires further investigation. The physical mechanism of charge injection in FeFETs is tunnelling, which occurs only when the barrier width is sufficiently thin and a significant density of states (DOS) for electrons (or holes) is available on the other side of the barrier.^24,25 An alternative approach for suppressing charge injection and enhancing FeFET endurance involves significantly reducing the DOS of the FE–IL interface—a strategy that has received little attention so far.

In this work, we propose a novel approach for improving the endurance of HfO₂-based FeFETs. Specifically, we introduce a monolayer GR layer between the FE layer and the IL of the FeFET. This GR layer not only reduces the E_IL by increasing the number of ferroelectric domains in the FeFET but also suppresses charge injection effects due to its inherently low DOS. Furthermore, a novel FeFET with a monolayer GR inserted in the gate oxide named a GR-FeFET was fabricated for the first time. Through a combination of simulation analysis, high-resolution transmission electron microscopy (HRTEM), differential phase contrast scanning transmission electron microscopy (DPC-STEM), and electrical characterization, we conducted an in-depth investigation into the ferroelectric domain states of HZO in the gate dielectric and the electrical characteristics of the GR-FeFET.

2. Mechanism and simulation

Monolayer GR can be regarded as a metal when physical processes unrelated to the DOS, such as charge injection, are not involved. The IL lacks ferroelectric properties and can be modeled as a conventional dielectric layer (DE). To assess the impact of the GR interlayer on the domain state of the FE film, we established ferroelectric–metal and ferroelectric–dielectric contact systems, as shown in Fig. 1(a). By solving the Laplace equation based on a two-dimensional anti-parallel domain model,^26,27 we obtained the potential distribution within the ferroelectric film for both contact systems. By comparing the electrostatic energy of the systems, we can determine the relative amount of electric domains. The basic equations and boundary conditions are shown in Fig. 1(b). The most significant difference between the ferroelectric–metal contact system and the ferroelectric–dielectric contact system lies in the interface charge density. For the ferroelectric–metal contact system, the metal unifies the interface potential, leading to a uniform charge distribution. In contrast, for the ferroelectric–dielectric contact system, the presence of electric domains results in an alternating charge distribution along the x-axis. In Fig. 1(b), ε_x and ε_z represent the dielectric constants of the FE layer in the x and z directions, while φ_f and φ_d represent the potential of the FE layer and the dielectric (DE) layer, respectively. The two-dimensional potential distribution obtained from the simulation is shown in Fig. 1(c). For the ferroelectric–dielectric contact system, the presence of electric domains causes a distributed interface potential with stray fields. The stray fields introduce extra electrostatic energy that scales with the number of electric domains. Therefore, the ferroelectric–dielectric contact system is not conducive to the stable existence of a large number of electric domains. In contrast, the inserted metallic layer in the ferroelectric–metal interface unifies the surface potential and eliminates stray electric fields. This condition lowers the energy caused by multi-domain states, thus increasing the number of domains. Therefore, introducing monolayer GR between the FE layer and the IL of the FeFET can effectively enhance the number of ferroelectric domains.

Fig. 2(a) and (b) show the device structures and band diagrams of a conventional FeFET and a GR-FeFET, respectively. From the band diagrams, it can be observed that an increase in the number of ferroelectric domains implies a reduction in the net charge density at the boundary between the FE layer and the IL. The lower net charge density at the ferroelectric layer and the IL interface in the GR-FeFET results in a reduced E_IL in the GR-FeFET compared to that in the conventional FeFET. Notably, the charge injection from the channel to the FE–IL boundary (where graphene is located) relies on the tunneling effect. This process not only requires a reduced effective barrier width but also necessitates the presence of available states in the GR layer. On the one hand, the introduction of monolayer GR increases the number of ferroelectric domains within the FE layer, resulting in a reduced equivalent E_IL and a wider effective tunneling barrier width, significantly weakening the charge injection effect. On the other hand, due to the low DOS in monolayer GR,^28,29 once the total charge injected into the GR layer approaches saturation, tunneling becomes prohibited, making further charge injection difficult. Consequently, under the combined influence of these two mechanisms, the charge injection effect in the GR-FeFET is better suppressed, suggesting that this device is likely to exhibit enhanced endurance characteristics.

3. Experimental

To verify the optimization effect of the GR interlayer on FeFET endurance, both a GR-FeFET and a conventional FeFET were fabricated. Indium–gallium–zinc oxide (IGZO) was selected to serve as the channel, while HZO (10 nm) and Al₂O₃ (3 nm) grown by atomic layer deposition (ALD) were employed as the FE layer and the equivalent IL, respectively. The fabrication process flows and device structures for the GR-FeFET and the conventional FeFET are shown in Fig. 3(a), (b), (c), and (d), respectively. For the GR-FeFET, first, the natural oxide layer on the surface of the heavily doped Si substrate was removed using HF solution. Then, a 10 nm thick ferroelectric HZO film was deposited on the Si substrate using an ALD process. A 30 nm thick TiN stress layer was sputtered onto the HZO layer, followed by rapid thermal annealing (RTA) at 550 °C for 90s under an N₂ atmosphere to tune the ferroelectric properties of the HZO film. Subsequently, the TiN stress layer was removed using a mixture of hydrogen peroxide and ammonia solution (H₂O₂:NH₃·H₂O:H₂O = 1:1:5). A monolayer GR was grown on a (111)-oriented Cu/sapphire substrate by chemical vapor deposition (CVD) at 1000 °C and transferred onto the HZO layer. Next, an additional 3 nm thick Al₂O₃ film was grown as an equivalent IL by an ALD thermal process. Following this, a 40 nm thick IGZO oxide semiconductor was deposited on the Al₂O₃ layer via sputtering and then patterned by a lift-off process. Subsequently, 50 nm thick Al was sputtered onto the semiconductor to form the source and drain electrodes, which were also patterned by a lift-off process. Finally, Al was sputtered onto the backside of the silicon substrate to serve as a gate electrode. Except for the growth and transfer of graphene, the fabrication process for the conventional FeFET is identical to that of the GR-FeFET.

With the recent advancements in TEM technology, DPC-STEM is now frequently used to observe the domain structure and distribution in ferroelectric films.^30,31 Cross-sectional TEM samples of both the GR-FeFET and the conventional FeFET were fabricated by a focused ion beam (FIB) process. A Thermo Scientific Themis Z spherical aberration correction TEM with an accelerating voltage of 200 kV, equipped with a four-quadrant detector and 4k × 4k pixelated detectors, was selected for material characterization.

Electrical characterization of the GR-FeFET and the conventional FeFET was performed using a Keysight B1500A semiconductor parameter analyzer. We primarily measured and compared the transfer characteristics, endurance, and gate leakage currents after cyclic PRG/ERS for both types of devices.

4. Results and discussion

The cross-sectional TEM images of the fabricated GR-FeFET and the conventional FeFET are shown in Fig. 3(c) and (f), respectively. To ensure the quality of the GR layer, we performed Raman spectroscopy analysis after transferring the GR, with the results shown in Fig. 3(g). The strong G′ peak at 2681 cm⁻¹ and the weak G peak at 1587 cm⁻¹ verify that the GR is monolayer in thickness. The absence of D and D′ peaks indicates a low defect density in monolayer GR.^32,33 Fig. 3(h) shows the cross-sectional energy dispersive spectroscopy (EDS) map image of the GR-FeFET. The line-shape carbon signal between the HZO and Al₂O₃ layers indicates the presence of GR, consistent with the designed device structure.

To visually observe the electric domain states within the ferroelectric HZO layers of the GR-FeFET and the conventional FeFET, DPC-STEM and HRTEM were used to examine the number and structure of the electric domains, respectively. In the ferroelectric HZO film, the polar phase is an orthorhombic phase, and the crystallographic structure allows for the presence of domain types of 90° and 180°.³⁴ The DPC-STEM images of the GR-FeFET and the conventional FeFET are shown in Fig. 4(a) and (b), respectively. HZO regions with different polarization orientations are mapped by different colors and labeled with numbers. The color positions that are relatively opposite (yellow and blue, red and cyan, and pink and green) represent a polarization orientation of approximately 180°. From Fig. 4(a) and (b), it is evident that the HZO layer in the GR-FeFET has a significantly higher number of ferroelectric domains compared to the conventional FeFET. Due to the localized nature of DPC-STEM as a micro-area characterization technique, we performed statistical analyses on the number of ferroelectric domains in multiple regions of both the GR-FeFET and the conventional FeFET, extracting the average domain size, as shown in Fig. S1.† From Fig. S1,† it can be observed that the number of ferroelectric domains in the HZO layer of the GR-FeFET is higher than that in the HZO layer of the conventional FeFET, and the domain size is smaller. This observation is consistent with the conclusions drawn from the analysis of Fig. 4. To further accurately determine the domain types, we performed HRTEM imaging on specific regions (the green dashed boxes in Fig. 4(a) and (b)) of the GR-FeFET and the conventional FeFET, as shown in Fig. 4(c) and (d). The insets in Fig. 4(c) and (d) show the fast Fourier transform (FFT) diffraction patterns corresponding to the blue dashed box regions and yellow dashed box regions, respectively. By analyzing the FFT diffraction patterns, we have marked the directions of the polar axes ([002] and [003]) for the ferroelectric HZO in regions 4 (5) and 5 (6) with blue and yellow lines, respectively. In Fig. 4(c), the polar axis ([002]) in region 4 and the polar axis ([003]) in region 5 are oriented at a 90° angle to each other, indicating that regions 4 and 5 are a pair of 90° domains. However, in Fig. 4(d), the polar axis ([003]) in region 5 and the polar axis ([003]) in region 6 are nearly collinear, indicating that regions 5 and 6 are a pair of 180° domains. The HRTEM results for the electric domain orientations are consistent with the DPC-STEM analysis results, thus supporting the credibility of domain mapping by DPC-STEM analysis, as shown in Fig. 4(a) and (b).

To confirm the ferroelectric properties of HZO thin films, we conducted Positive Up Negative Down (PUND) tests on the gate stack of the GR-FeFET, as depicted in the inset of Fig. 5(a). The observed remanent polarization is approximately 6 μC cm⁻², consistent with the typical ferroelectric characteristics of the HZO film. The transfer characteristic curves of the GR-FeFET and the conventional FeFET are shown in Fig. 5(a) and (b), respectively. The remanent polarization causes a counterclockwise hysteresis in the transfer characteristic curves. The maximum MW values for the GR-FeFET and the conventional FeFET are 0.3 V and 0.2 V, respectively. The waveform for the endurance test is shown in Fig. 6(a). A gate voltage sweeping from −0.5 V to 1.5 V is used for device reading. The transfer characteristic (drain current versus gate voltage (I_d–V_g)) curve of the GR-FeFET in Fig. 6(b) shows no hysteresis, suggesting no disturbance of the storage states with this read condition. Fig. 6(c) displays the PRG/ERS characteristics at ±2.5 V, along with the corresponding MWs (@I_d = 5 × 10⁻⁴ μA) for various pulse widths. Notably, the maximum MW of 0.15 V is achieved when the pulse width is set to 50 μs. Consequently, this PRG/ERS condition (±2.5 V, 50 μs) is applied for the endurance testing of the GR-FeFET.

The endurance test results are shown in Fig. 7(a) and (c). The MW of both FeFETs shows a trend of increasing and then decreasing over the course of the PRG/ERS operations. For the GR-FeFET, when the number of PRG/ERS cycles reaches 10⁸, the MW remains above 0.1 V. This represents a <33.3% degradation from the initial value (0.15 V), suggesting that the endurance of the GR-FeFET exceeds 10⁸ cycles. For the conventional FeFET, as the number of PRG/ERS operations reaches 10⁶, the MW reduces to just 0.04 V, which represents a 42.9% degradation from the initial value (0.07 V). This indicates an endurance over two orders of magnitude higher in the GR-FeFET than in the conventional FeFET. Fig. 7(b) and (d) display the leakage current (gate current versus gate voltage (I_g–V_g)) curves of the GR-FeFET and the conventional FeFET after endurance testing, respectively. For the GR-FeFET, the gate leakage current is mostly less than 10⁻⁵ μA, and reaches a maximum value of 2.13 × 10⁻⁵ μA at a gate voltage of 3.5 V. In the case of the conventional FeFET, the gate leakage current exceeds 10⁻⁵ μA when V_g sweeps above 1.5 V, and reaches 3.45 × 10⁻⁵ μA at 3.5 V. The lower gate leakage current in the GR-FeFET demonstrates that charge injection and capture are significantly suppressed in the GR-FeFET during the PRG/ERS operations. This phenomenon can be attributed to the reduction of the E_IL and the suppression of tunneling effects by the low DOS of the monolayer GR.

Fig. 8 summarizes the operation voltages and endurance characteristics of various channel FeFETs reported in the recent literature. The green region in the lower right corner represents the ideal properties of FeFETs. From the figure, it is evident that compared to Si-channel FeFETs with optimized interfacial layers, the proposed GR-FeFET in this work demonstrates significantly better endurance. Furthermore, even compared to other oxide-channel FeFETs without interfacial layers, the GR-FeFET exhibits comparable or even superior performance in terms of both operating voltage and endurance. This demonstrates the high potential of GR-FeFETs for applications in low-power, high-endurance memory devices.

5. Conclusions

In this study, we propose a novel approach for enhancing the endurance of FeFETs by introducing monolayer GR between the FE layer and the IL of a conventional FeFET. To validate the feasibility and effectiveness of this strategy, we fabricated a GR-FeFET and a conventional FeFET, and conducted in-depth investigations of the domain states in the HZO layer and the device characteristics of both types of devices. Simulation analyses and HRTEM and DPC-STEM material characterization studies revealed that the incorporation of monolayer GR reduces the electrostatic energy caused by stray electric fields, thereby increasing the number of domains in the FE layer. Band structure analysis indicates that the increase in domain numbers effectively reduces the net charge density at the FE–IL interface, thereby lowering the E_IL. Moreover, the low DOS characteristic of monolayer GR suppresses the tunneling of channel charges to the FE–IL interface. Under these dual mechanisms, the charge injection effect in the GR-FeFET is significantly suppressed, leading to enhanced endurance. Electrical measurements show that the gate current of the GR-FeFET after multiple PRG/ERS cycles is lower than that of the conventional FeFET, confirming effective suppression of charge injection. Furthermore, the endurance and degradation rates of the GR-FeFET are superior to those of the conventional FeFET, consistent with the simulation, material characterization, and band structure analysis results. Our work offers an innovative perspective and pathway for designing high-endurance FeFETs for next-generation embedded memory applications.

Data availability

The data that support the plots and findings of this study are available from the corresponding authors upon reasonable request.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by the National Key R&D Program of China (2022YFB4400300), the National Natural Science Foundation of China (62274003, 61927901, 92164203, and 62404010), the 111 Project (B18001), and in part by the STIC under Grant QYJS-2022-1501-B. The authors would like to thank the staff of the National Micro/Nano Fabrication Laboratory of Peking University for their assistance in device fabrication.

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d5nr02579f

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