Single-layer HfN₂: symmetric scaling behavior in CMOS transistors†

Xianghe Liu^a and Yuliang Mao*^abc
aHunan Key Laboratory for Micro–Nano Energy Materials and Devices, School of Physics and Optoelectronics, Xiangtan University, Xiangtan 411105, China. E-mail: ylmao@xtu.edu.cn
^bNational Center for Applied Mathematics in Hunan, Xiangtan University, Xiangtan 411105, China
^cState Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, 865 Changning Road, Shanghai 200050, China

First published on 11th July 2025

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Two-dimensional (2D) semiconductors have emerged as competitive channel materials for multifunctional, highly integrated micro-nanoelectronic devices.^1–7 Their atomically thin and smooth surfaces without charge traps enable better gate control, while their high electron and hole mobilities enhance the ON-state current (I_on) of complementary metal-oxide-semiconductor (CMOS) transistors, thereby advancing Moore's law into the sub-5-nm regime.^8,9 For instance, Desai et al.¹⁰ demonstrated that field-effect transistors (FETs) using bilayer MoS₂ channels can scale physical gate lengths (L_g) down to 1 nm. Recently, Jiang et al.¹¹ achieved an 83% room-temperature ballistic ratio and a transconductance (g_m) of 6 mS μm⁻¹ in InSe FETs fabricated via Y-doping induced phase transition. These results surpass the performance of the state-of-the-art Si-based FETs and confirm that 2D FETs can deliver practical performance close to theoretical predictions.

CMOS transistors are the cornerstone of large-scale integrated circuits (ICs), consisting of paired N- and P-type MOSFETs that manage signal processing and logic operations.^12–14 Imbalanced signal transmission and amplification can result from poor or asymmetric performance between NMOS and PMOS transistors.^15,16 While existing studies primarily focus on individual device compliance with the International Technology Roadmap for Semiconductors (ITRS) high-performance (HP) or low-power (LP) standards, little attention has been given to symmetry in performance metrics.^17–23 Achieving highly symmetric NMOS and PMOS performance under ITRS standards requires 2D materials with both high electron and hole mobility. This presents a challenge, particularly at ultra-short scales.

Recently, transition metal nitride semiconductors have attracted significant attention due to their excellent physicochemical properties.^24–27 For instance, few-layer HfS₂ FETs exhibit remarkable field-effect behavior, with an I_on/I_off ratio of ≈10⁷.²⁸ Single-layer (SL) HfSe₂ is considered a promising candidate for 2D transistors due to its moderate band gap and the presence of a native high-κ dielectric (HfO₂).^29,30 As a member of this family, SL HfN₂ has been demonstrated to be kinetically, mechanically, and thermodynamically stable.³¹ Moreover, HfN₂ possesses exceptionally high electron and hole mobilities, approximately 10³ cm² V⁻¹·s⁻¹, and is a promising candidate for microelectronic devices.^31–33 Consequently, the performance of its corresponding NMOS and PMOS devices exhibits the potential to achieve excellent symmetry at sub-5 nm ultra-short scales and satisfy ITRS targets.

In this study, we employed first-principles quantum transport methods to investigate the transport properties of SL HfN₂ in CMOS transistors. Our findings reveal that SL HfN₂ NMOS and PMOS transistors can be scaled down to L_g = 3 nm while meeting ITRS-HP standards. At sub-5-nm-L_g scales, the ratio of key quality factors between NMOS and PMOS falls within the range of 0.5–1.5, indicating excellent symmetry. These results highlight SL HfN₂'s potential as a fundamental block for next-generation highly integrated and miniaturized nanoelectronic devices.

The atomic structure of single-layer (SL) HfN₂, shown in Fig. 1(a), consists of a hexagonal unit cell where a hafnium (Hf) atom is sandwiched between two nitrogen (N) atoms. This structure has been reported to be both kinetically and thermodynamically stable.³¹ After optimization, the lattice constant is determined to be a = b = 3.414 Å, closely matching previous reports (a = 3.419 Å,³⁴ a = 3.42 ų⁵). The calculation methods are described in the ESI.† Fig. 1(b) reveals that HfN₂ exhibits a direct bandgap of 1.346 eV, with the conduction band minimum (CBM) and valence band maximum (VBM) predominantly contributed by Hf and N atoms, respectively, as further confirmed by Fig. 1(c). Based on equation and fitting the band dispersion from Fig. 1(b), the electron and hole effective masses for SL HfN₂ are calculated as 0.575 and 0.766m₀, respectively. Fig. 1(d) illustrates the schematic of the dual-gate SL HfN₂ MOSFETs. For both NMOS and PMOS simulations, the source/drain electrodes are heavily doped N- and P-type, while the central scattering region remains intrinsic. The HfN₂ channel is encapsulated by SiO₂ dielectric layers (thickness: 4.1 Å; dielectric constant: 3.9), with symmetric top and bottom metal gates modulating the barrier height in the intrinsic region. Furthermore, an underlap (L_UL) structure is introduced to mitigate short-channel effects caused by physical gate length scaling.³⁶

The key quality factors (KQF) for HfN₂ N(P)MOS transistors include ON-state current (I_on), transconductance (g_m), subthreshold swing (SS), delay time (τ), power-delay product (PDP), and total capacitance (C_g), as shown in the calculations in the ESI.† According to the 2013 ITRS criteria for sub-5-nm-L_g FETs, the required I_on for high-performance (HP) and low-power (LP) applications is ≥900 μA μm⁻¹ and 295 μA μm⁻¹, respectively, while the OFF-state current (I_off) should be ≤0.1 μA μm⁻¹ for HP and ≤5 × 10⁻⁵ μA μm⁻¹ for LP.³⁷ The g_m and SS denote the gate control capability of CMOS transistors in the superthreshold and subthreshold regions, respectively. Moreover, the τ, PDP, and C_g describe the switching time, power dissipation, and total capacitance, respectively.

To achieve high I_on, steep SS, and excellent symmetry, the I–V_g curves for NMOS and PMOS transistors were first evaluated at four doping concentrations (N_e/h = 1 × 10²⁰, 5 × 10²⁰, 1 × 10²¹, 2 × 10²¹ cm⁻³), as shown in Fig. S1(a) and (b) (ESI†) of the ESI.† At low doping (N_e/h = 1 × 10²⁰ cm⁻³), both NMOS and PMOS exhibit minimal SS (60.4 and 50.6 mV dec⁻¹) but fail to achieve sufficient saturation current to fulfill ITRS-HP or -LP standards (see Table 1). For high doping (N_e/h = 2 × 10²¹ cm⁻³), the saturation current increases significantly, but the SS also worsens, necessitating higher gate voltages to turn off the transistor, thereby reducing I_on. After balancing I_on and SS, a doping concentration of N_e/h = 5 × 10²⁰ cm⁻³ was selected to study the performance limits of SL HfN₂ NMOS and PMOS transistors. Additionally, at all four concentrations, the I_on for L_g = 5 nm NMOS and PMOS transistors fails to meet the ITRS-LP requirements (I_on ≥ 295 μA μm⁻¹). Given that transistor performance generally degrades as gate length shortens, we do not pursue further simulations on ITRS-LP applications for SL HfN₂ NMOS and PMOS transistors.

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Fig. S1(c) and (d) (ESI†) present the I–V_g characteristics for SL HfN₂ NMOS and PMOS devices with L_g = 5–1 nm and L_UL = 0 nm. Notably, the I–V_g curves between NMOS and PMOS exhibit excellent symmetry, which enhances the efficiency of CMOS logic operations. As L_g decreases from 5 to 1 nm, the saturation current of SL HfN₂ N(P)MOS increases, but gate control weakens. This is attributed to the proximity of the source and drain depletion regions, leading to significant drain-induced barrier lowering (DIBL). For example, L_g = 1nm N(P)MOS is unable to control the drain current by increasing the gate voltage, and the device undergoes a source-drain punchthrough phenomenon, causing transistor failure. For ITRS-HP applications (I_on ≥ 900μA μm⁻¹), SL HfN₂ transistors without an L_UL structure outperform the I_on requirement at L_g = 5nm (I_on = 1864.71μA μm⁻¹ for NMOS and 1638.24μA μm⁻¹ for PMOS), but fail to at L_g = 3–1nm.

To mitigate the DIBL effect caused by shrinking L_g, a symmetric L_UL structure is introduced between the gate and drain (source). The I–V_g curves of SL HfN₂ N(P)MOS transistors with L_g = 5–1 nm and L_UL = 0–4 nm are shown in Fig. S2 (ESI†). It can be found that the I–V_g curves between NMOS and PMOS exhibit strong symmetry under the same L_UL and L_g. While the L_UL structure has little impact on transistors at L_g = 5 nm, it significantly helps devices with L_g = 3–1 nm meet the OFF-state current requirement for HP applications (I_off ≤ 0.1 μA μm⁻¹). Tables S1 and S2 (ESI†) summarize key quality factors (KQF) for NMOS and PMOS devices, including I_on, SS, I_on/I_off, PDP, τ, g_m, and C_g, as shown in the ESI.†

To understand the physical mechanism by which the L_UL structure modulates the I–V_g characteristics of the transistor, we analyze the case of SL HfN₂ NMOS at L_g = 3 nm, as shown in Fig. 2(a). When L_UL = 0 nm, applying a gate voltage of −0.7 V effectively turns off the device's drain-source current (I_ds) for HP applications. As L_UL increases, the subthreshold swing becomes steeper, and the gate voltage required to turn off I_ds gradually decreases. Fig. 2(b) reveals that at L_UL = 2 nm, the HfN₂ NMOS with L_g = 3 nm achieves an optimal I_on of 1338.24 μA μm⁻¹, exceeding the ITRS-HP requirements. However, further increasing or decreasing L_UL weakens I_on.

To gain insights into the effect of the L_UL structure on I_on, the local density of states (LDOS) and transmission spectra were calculated for devices with L_UL = 0–3 nm, as shown in Fig. 3. The effective barrier variation (ΔΦ_B) during the switch from OFF-state to ON-state is described by ΔΦ_B = Φ_B-off − Φ_B-on, where Φ_B-off and Φ_B-on represent the barrier height between the source potential (μ_s) and the maximum conduction band energy (E_max) in the OFF-state and ON-state, respectively.³⁸ Below E_max, the current is dominated by carrier tunneling (I_tunneling), while above E_max, it is driven by thermionic emission (I_therm).

Changing the L_UL structure can influence the I_on of transistors through three primary factors. First, increasing the L_UL length enhances ΔΦ_B, leading to a reduction of SS, as illustrated in Fig. 2(c). A smaller SS allows the transistor to switch to the ON-state more rapidly under the same supply voltage, thereby improving I_on. Second, extending the L_UL length raises the proportion of I_therm in the total current. As L_UL varies from 0 to 3 nm in the OFF-state, E_max gradually approaches μ_s while the channel barrier width (w) becomes significantly wider. This leads to an increase in I_therm and a decrease in I_tunneling .³⁹ In the ON-state, Φ_B decreases from 0 to −0.29 eV, indicating that carriers can traverse the transistor channel barrier-free, which I_on supplied by I_therm. Finally, for a fixed L_g, excessively long L_UL can reduce the device's I_on. Increasing L_UL length decreases the L_g/L_UL ratio, which diminishes the probability of carrier transmission within the bias window [μ_s, μ_d], resulting in reduced I_on. A comparison of Fig. 2(c) and Fig. 3(j) reveals that while SS remains relatively unchanged when L_UL increases from 2 to 3 nm, the transmission coefficient declines significantly. Therefore, optimizing the L_UL structure is essential for achieving optimal I_on.

To evaluate the KQF, including I_on, SS, PDP, τ, g_m, and C_g for the N(P)MOS devices, the maximum I_on of SL HfN₂ transistors is compared with BAs, MoS₂, MoTe₂, and MoSi₂N₄ transistors.^21–23,40 As shown in Fig. 4(a) and (b), L_g = 5–1 nm HfN₂ NMOS devices exhibit higher I_on than MoS₂ counterparts. At L_g = 5 and 3 nm, the I_on for HfN₂ PMOS reaches 1638.24 and 1614.71 μA μm⁻¹, significantly exceeding those of MoS₂, MoTe₂, and MoSi₂N₄, nearly doubling the ITRS-HP target. Notably, the I_on ratio for HfN₂ NMOS and PMOS ranges from 0.82 to 1.39 in the sub-5-nm-L_g region, demonstrating excellent symmetry. Detailed I_on variations across different L_g values for SL HfN₂ N(P)MOS transistors are presented in Fig. S3(a) and (b) (ESI†). As L_g decreases from 5 to 1 nm, the optimal I_on values for N(P)MOS devices range from 1864.71–329.41 μA μm⁻¹ (1638.24–279.12 μA μm⁻¹). Importantly, at L_g = 5 and 3 nm, the I_on of N(P)MOS devices with appropriate L_UL lengths surpass the ITRS-HP requirements.

The SS is one of the KQFs that quantifies the gate control efficiency in CMOS transistors, derived from equation . Fig. 4(c) and (d) show that the optimal SS for SL HfN₂ N(P)MOS devices ranges from 78.94 to 127.1 mV dec⁻¹ (54.52 to 116.78 mV dec⁻¹) for L_g = 5–1 nm. Across different L_g, the SS of HfN₂ NMOS devices is consistently higher than MoS₂, MoTe₂, and MoSi₂N₄ counterparts, while PMOS devices exhibit lower SS compared to BAs. Notably, the SS of L_g = 5 nm HfN₂ PMOS transistors aligns with that of MoS₂ and MoSi₂N₄, breaking the thermal limit of 60 mV dec⁻¹.⁴¹ This indicates that the transistor current in ultra-short channels is composed of both I_therm and I_tunneling. Moreover, Figs. S3(c) and (d) (ESI†) illustrate the detailed SS variation for L_g = 5–1 nm and L_UL = 4–0 nm SL HfN₂ transistors. The SS of N(P)MOS devices increases from 78.94 to 1053.87 mV dec⁻¹ (54.52 to 832.15 mV dec⁻¹) as L_g and L_UL decrease, showing a 92.5% (93.4%) raise. This significant increase is attributed to the DIBL effect, even leading to the source-drain punchthrough phenomenon.

The smaller the values of τ and PDP, the faster the switching speed and the lower the power consumption for CMOS ICs, as determined by Equations and PDP = C_gV_ds² = V_dsI_onτ (see the calculation methodology for ESI†). Fig. S4(a) and (b) (ESI†) show that the optimal τ values for SL HfN₂ N(P)MOS transistors with L_g = 5–1 nm consistently satisfy the ITRS-HP target (τ ≤ 0.423 ps). For NMOS devices, τ ranges from 0.055 to 0.088 ps, and for PMOS, from 0.079 to 0.134 ps, both outperforming MoS₂ and MoTe₂ counterparts. Fig. S4(c) and (d) (ESI†) illustrate that the optimal PDP values for HfN₂ NMOS and PMOS transistors increase linearly with L_g, falling within the ranges of 0.012–0.092 fJ μm⁻¹ and 0.016–0.102 fJ μm⁻¹, respectively, exhibiting excellent symmetry. Additionally, the detailed variations in τ, PDP, C_g, and g_m for SL HfN₂ NMOS and PMOS devices across L_g = 5–1 nm and L_UL = 0–4 nm are plotted in Fig. S5 and S6 (ESI†). All transistors satisfy the ITRS-HP targets for τ, PDP, and C_g, except for the τ value of the NMOS device at L_g = 3 nm and L_UL = 0 nm. Moreover, the g_m for NMOS devices ranges from 2.04 to 9.44 mS μm⁻¹, while for PMOS devices, it falls between 1.24 and 8.12 mS μm⁻¹, demonstrating strong symmetry in performance. Notably, HfN₂ devices exhibit extreme sensitivity to channel length variations at sub-5 nm gate lengths L_g, which may introduce significant noise challenges for large-scale integration. To address this issue, performance stability could be enhanced through optimized gate dielectric engineering, improved process integration, refined device design, and strategic strain engineering approaches.^42–44

The efficient operation of CMOS ICs requires good symmetry between NMOS and PMOS transistors to ensure fast signal processing and logic operations. Fig. 5(a) and (b) demonstrate the optimal I_on and SS symmetry between SL HfN₂ NMOS and PMOS for L_g = 5–1 nm, compared to BAs, MoS₂, MoTe₂, and MoSi₂N₄ counterparts. For sub-5-nm-L_g, the I_on ratio between HfN₂ NMOS and PMOS devices ranges from 0.82 to 1.39, superior to the symmetry of other devices. The SS ratio for L_g = 3–1 nm is 0.94–1.11, retaining optimal symmetry. Furthermore, the symmetry in the τ and PDP values is 0.49–0.93 and 0.75–0.90, respectively, as shown in Fig. S7(a) and (b) (ESI†), outperforming that of BAs transistors. The KQF ratios suggest that SL HfN₂ is ideal for building highly symmetric homogenous CMOS IC modules.

Additionally, Fig. 5(c) illustrates the relationship between I_on and effective mass (m*) for transistors with L_g = 5 nm, based on different channel materials.^{21–23,40,45–47} The I_on initially decreases and then increases, similar to observations in WSe₂ and silicane.^17,48 This behavior is attributed to the fact that extremely small and large m* enhance carrier transport velocity and band edge density of states, respectively, which in turn effectively improves I_on.

We also discussed whether HfN₂ has a corresponding native oxide layer, as shown in Fig. S9 (ESI†). First, oxygen adsorption on the HfN₂ surface has been examined at three representative sites—top, bridge, and hollow positions. The adsorption energies at these sites were computed to identify the most favorable location for the formation of a native oxide layer. After structural relaxation, oxygen atoms at all three initial positions converge to the top site configuration, with a corresponding adsorption energy of ΔE_ad = E_HfN2+O2 − E_HfN2 − E_O2 ≈ −3.34 eV, as shown in Fig. S9(a) and (b) (ESI†). Second, based on the oxygen adsorption model at the top site, the static dielectric constant was calculated. The result shows an increase of approximately 4 in the static dielectric constant compared to the pristine HfN₂. This suggests that full oxidation of HfN₂ may lead to a significantly enhanced dielectric constant, potentially comparable to that of HfO₂, making it a promising candidate as a native high-κ gate dielectric for HfN₂-based channel materials. Next, a HfN₂/oxide interface model was constructed, as shown in Fig. S9(c) (ESI†). The interface is found to be weakly van der Waals bonded with no significant interface state accumulation, indicating good integration potential. Finally, ab initio molecular dynamics (AIMD) simulations of monolayer HfN₂ were performed at 300 K. As illustrated in Fig. S9(d) (ESI†), the total energy exhibits reasonable fluctuations over a 5 ps time scale, and no structural reconstruction is observed, confirming the good thermal stability of HfN₂.

In summary, we employ density functional theory combined with the nonequilibrium Green's function method to predict the performance of SL HfN₂ NMOS and PMOS transistors at sub-5-nm-L_g scales. The results demonstrate that even when L_g is reduced to the 3 nm limit, the key quality factors (KQFs) of HfN₂ NMOS and PMOS transistors still surpass the benchmarks set by ITRS-HP. By calculating the LDOS and transmission spectra of HfN₂ FETs with L_UL = 0–3 nm, the physical mechanisms by which the L_UL structure regulates the I_on are elucidated. Importantly, NMOS and PMOS transistors with L_g ranging from 5 to 1 nm exhibit exceptional symmetry, that is, I_on, SS, τ, and PDP ratios between 0.5 and 1.5, which is superior to other reported 2D transistors. These findings underscore physical insights and strategic interventions for achieving optimal KQFs in ultra-short channel HfN₂ FETs and offer theoretical guidance for the development of symmetric, high-performance CMOS transistors.

Conflicts of interest

The authors declare no competing financial interests.

Data availability

The data that support the findings of this study are available within the article and its ESI.†

Acknowledgements

This research is funded by Natural Science Foundation of Hunan Province, China (Grant No. 2023JJ30567) and the Graduate Research Innovation Project of Hunan Province (Grant No. CX20230636).

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Footnote

† Electronic supplementary information (ESI) available: Computational methods; I–Vg characteristics of SL HfN2 N(P)MOS at different doping concentrations, Lg, and LUL; Ion and SS of HfN2 N(P)MOS; optimal τ and PDP of HfN2 transistors compared to those reported for armchair-BAs, MoS2, MoTe2, and MoSi2N4 transistors; the τ, PDP, Cg, and gm of HfN2 N(P)MOS devices with different Lg and LUL; symmetry of τ and PDP between NMOS and PMOS; and detailed data on all KQFs of sub-5-nm-Lg SL HfN2 N(P)MOS. See DOI: https://doi.org/10.1039/d5tc01623a

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