Ab initio quantum transport simulation of the sub-1 nm gate-length monolayer and bilayer α-MoTe₂ field-effect transistors

Mudasser Husain^a, Younas Ahmed^a, Xingyue Yang^a, Shibo Fang^g, Zongmeng Yang^a, Jichao Dong^a, Linqiang Xu^a, Nasir Rahman^b and Jing Lu*^acdef
aState Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871, P. R. China. E-mail: jinglu@pku.edu.cn
^bDepartment of Physics, University of Lakki Marwat, Lakki Marwat, KPK, Pakistan
^cCollaborative Innovation Center of Quantum Matter, Beijing 100871, P. R. China
^dBeijing Key Laboratory for Magnetoelectric Materials and Devices, Beijing 100871, P. R. China
^eBeijing Key Laboratory for Magnetoelectric Materials and Devices (BKL-MEMD), Peking University, Beijing 100871, P. R. China
^fPeking University Yangtze Delta Institute of Optoelectronics, Nantong 226010, P. R. China
^gScience, Mathematics and Technology (SMT) Cluster, Singapore University of Technology and Design, 487372, Singapore

First published on 30th June 2025

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1. Introduction

Transistor technology has played a pivotal role in advancing modern electronics.¹ The crucial driving force behind the advancement and miniaturization of modern electronics adheres to the scaling principle of Moore's law.² Moore's law predicted that the number of transistors per square centimeter in integrated circuits (ICs) doubles every two years, which increases computing power and lowers cost. Since the invention of the first point-contact transistor in 1947, transistor technology has continuously evolved, leading to the development of silicon-based Fin field-effect transistors (FinFETs) designed to address the need for smaller, faster, and more energy-efficient devices.^3,4 The mainstream Si-FinFETs show improved device performance relative to conventional planar transistors.⁵ However, as the gate-length approaches 10-nm, the Si-FinFETs suffer from short-channel effects (SCEs), which reduce gate controllability.⁴ This results in increased leakage currents, leading to higher power consumption. Additionally, the limited carrier mobility of Si due to the intrinsic scaling limits restricts switching speeds, thereby hindering the overall performance of the ultra-scaled Si-transistors. Incorporating new structure transistors, alternative channel materials, or new principle transistors is imperative to overcome these challenges and sustain Moore's law life.^6–8

2D semiconductors, notably TMDCs, have emerged as promising alternative channel materials for the ultra-scaled MOSFETs, playing a crucial role in advancing next-generation electronic devices.^9,10 The atomic-layer thickness of the TMDC materials provides exceptional electrostatic control and effectively mitigates SCEs. In TMDCs, the smooth surfaces and absence of out-of-plane dangling bonds lead to high carrier mobility, thereby enhancing the performance of the device.¹¹ Furthermore, the atomic-layer stacking-dependent tunable band gap of 2D materials enables the development of more energy-efficient transistors tailored to advanced technology nodes.^12,13 In TMDCs, the MoTe₂ exists in two stable phases, semiconducting 2H and semimetallic 1T′. There is a minimal energy difference (typically <0.1 eV per atom) between its 2H and 1T′ phases, enabling reversible and controllable phase transitions crucial for phase-engineered nanoelectronic devices.¹⁴ The semiconducting α-MoTe₂ featuring a moderate band gap of 1.1 eV in the ML, similar to silicon (1.1 eV), stands out as a promising channel material for field-effect transistors. The moderate bandgap is more suitable for low-voltage operation and high on-state current, striking a balance between sufficient carrier injection of either electrons for n-FETs or holes for p-FETs. This balance underscores the unique potential of MoTe₂ as a channel material for ultra-scaled transistor technologies compared to other 2D TMDCs. MoTe₂ exhibits highly ambipolar and tunable polarity-controllable transport, attributed to its more symmetric band alignment and reduced Schottky barrier heights for both electrons and holes. This tunability makes MoTe₂ particularly promising for reconfigurable and complementary logic devices, where both n-type and p-type transistors can be realized by selecting appropriate metal contacts.

In transistors, scaling down the gate-length (L_g) has been a key focus for researchers aiming to push the limits of device miniaturization.^7,15,16 In 2022, Fan Wu et al.¹⁷ fabricated side-wall MoS₂ transistors using a single graphene-layer-edge as the gate electrode, achieving an ultra-short physical gate length of 0.34 nm. These devices exhibited subthreshold swing (SS) values as low as 117 mV dec⁻¹ and a current on/off ratio (I_on/I_off) of up to 1.02 × 10⁵, highlighting the potential for continued scaling of transistors following Moore's law. However, despite the aggressive gate downscaling, these transistors suffer from limited I_on, primarily due to a relatively long channel, thick gate dielectric, and Schottky barriers at the metal-semiconductor interface. In addition to experiments, ab initio quantum simulations of the double-gated n- and p-type ML MoS₂ transistors featuring a gate-length of 0.34 nm have been reported in 2024 by Ying Li et al.,¹⁸ demonstrating superior performance to the 1-nm gate-length ML MoS₂ transistors. In 2025, Xingyue Yang et al.¹⁹ reported the ML and BL WSe₂ p-FETs with a gate-length of 0.34 nm, utilizing ab initio quantum transport simulations to assess their performance. The ML WSe₂ p-FETs, with a channel length of less than 5 nm, achieve a high I_on of 712 μA μm⁻¹, in line with the ITRS standard requirement for HP devices. In contrast, the BL WSe₂ p-FETs show a 40% reduction in I_on, attributed to changes in the band structure and degradation of gate control. Theoretical and experimental research on the sub-1 nm L_g transistors based on other 2D TMDC materials is also highly anticipated.

Many researchers reported the n- and p-type transistors based on the ML and multilayer α-MoTe₂ for HP and LP devices.^20–22 Notably, Qi Zhang et al. have demonstrated state-of-the-art 1T′-2H heterophase bilayer MoTe₂ FETs with a gate length of 4 nm, achieving excellent switching behavior, including a subthreshold swing of ∼73 mV decade⁻¹ and an on/off current ratio of ∼10⁵.²³ Qiang Li et al.²⁴ recently used ab initio quantum transport simulations to evaluate the ultimate performance of the ML α-MoTe₂ n- and p-type transistors down to 1-nm gate-length for HP and LP device applications. They found that the I_on of the 3-nm gate-length p-type ML α-MoTe₂ transistor meets the ITRS standard for both HP and LP applications. Although 2D α-MoTe₂ is regarded as a promising alternative channel material for the n- and p-type FETs down to 1-nm gate-length, this material remains unexplored for the sub-1 nm gate-length transistors. It remains a topic of research interest in terms of three challenges. (1) What is the fundamental scaling limit of the ML and BL α-MoTe₂ FETs? (2) Does the ultimate performance of the ML and BL α-MoTe₂ FETs meet the ITRS requirements? (3) Does the ML and BL α-MoTe₂ exhibit superior performance to the most studied ML MoS₂ for FETs with sub-1 nm gate-length scale?

In this research, we aim to address these three challenges by performing ab initio quantum transport simulation of the n- and p-type MOSFET with the 0.34 nm gate-length based on the ML and BL α-MoTe₂ for HP and LP applications operating at an ultra-low supply voltage (V_dd) of 0.54 V. The 0.34 nm gate-length n-type transistor based on the ML α-MoTe₂ with a 2-nm underlap meets the ITRS standards for HP and LP applications. For the BL α-MoTe₂ transistor, we find that BL α-MoTe₂ exhibits an indirect band gap due to interlayer coupling, leading to a flatter valence band and higher hole effective mass. This reduced band dispersion significantly limits carrier mobility, particularly for holes, thereby degrading the on-state current and overall device performance. These changes explain why BL α-MoTe₂ MOSFET configurations in particular fail to meet the ITRS standard for HP and LP applications. Therefore, the performance of the n-type ML α-MoTe₂ transistor is evaluated by calculating key figures-of-merit (FOMs) following the ITRS guidelines. The key FOMs include SS, transconductance, power delay product (PDP), and intrinsic delay-time (τ). This study explores the potential of ML α-MoTe₂ as a 2D nanochannel material for next-generation ultra-scaled FETs.

2. Device model and simulation methodology

We considered the two-probe and double-gated FET device model for the quantum transport simulations. A two-probe model comprises a central channel region attached to the two bulk electrodes, i.e., the left electrode (source) and the right electrode (drain).²⁵ The central channel region of the device usually characterizes the material under investigation. The left and right electrodes work as electrical terminals through which electrical signals are applied. Fig. 1 shows the configuration of our two-probe and double-gated device, in which the pristine 2D semiconducting ML/BL α-MoTe₂ are considered as the channel material. The electrode regions are heavily n- or p-type doped ML/BL α-MoTe₂ and act as source and drain terminals at the left and right portions. The source and drain electrodes are assumed to have bulk properties. Two metallic gates (top and bottom) of the 0.34 nm L_g are applied and separated from the channel region using the high-k HfO₂ as a gate-dielectric material. The effective oxide thickness (EOT) is maintained at 0.26 nm, as specified by the ITRS guidelines.^26,27 It is well known that in addition to EOT, the physical oxide thickness (T_OX) also plays a critical role in controlling short-channel effects (SCEs). The physical thickness of the oxide layer varies with the dielectric constant (k) to maintain a fixed EOT, as described by the relationship:²⁸ . For HfO₂, with a dielectric constant k_OX ≈ 25, and SiO₂ having k_SiO2 = 3.9, the resulting physical thickness T_OX of 1.66-nm is adjusted accordingly in the simulation. The underlap length (UL) refers to the physical distance between the edge of the gate electrode and the beginning of the source or drain region. A symmetrical UL is considered on both sides of the channel to realize uniform electrostatic control, mitigate SCEs, and enhance overall device performance.²⁹ In the quantum transport simulation of the device, the three spatial regions, i.e., source, drain, and channel, have Neumann and periodic boundary conditions along the x and y directions, respectively. In the transport z-direction, the source and drain regions act as equilibrium bulk materials having periodic boundary conditions, while in the channel region, the Dirichlet boundary conditions are considered.³⁰ A Dirichlet boundary condition is applied at the metallic gate electrode to set a defined potential. In contrast, Neumann boundary conditions are used in the dielectric region to represent electrically insulating boundaries.

The transport properties of the 0.34-nm L_g ML/BL α-MoTe₂ transistors are analyzed using the DFT + NEGF formalism^31,32 implemented within the advanced atomic-scale quantum Atomistix ToolKit (ATK) simulation package.³⁰ The ML and BL (AB-stacking) of the α-MoTe₂ are first optimized by considering a vacuum spacing of 20 Å along the out-of-plane direction to avoid artificial interactions of the period images. In geometry optimization, the limited memory Broyden–Fletcher–Goldfarb–Shanno (LBFGS) method is employed to relax the ML and BL α-MoTe₂. The calculations are considered fully converged when the force is below 0.01 eV Å⁻¹ and the stress error tolerance is within 0.001 eV Å⁻³, ensuring accurate and reliable results. A basis set of linear combinations of atomic orbitals (LCAO) with a density-mesh cutoff of 125 Hartree is regarded for our DFT calculations. To fully estimate the exchange and correlation interactions within the ML/BL α-MoTe₂, the generalized gradient approximation of the Perdew–Burke–Ernzerhof (GGA-PBE) functional is employed.³³ In the GGA-PBE functional, the state-of-the-art norm-conserving double-zeta-double-polarized PseudoDojo pseudopotentials are used for higher accuracy of calculations.³⁴ The GGA-PBE exchange–correlation functional is widely used in ab initio quantum transport simulations and remains effective in the band gap renormalization in FETs due to two key factors. First, the dielectric region in the device contributes to the screening of electron–electron interactions by modifying the electrostatic environment in the channel, which weakens the Coulomb repulsion between charge carriers.³⁵ Second, the doped semiconducting channel in transistors contains a high concentration of free electrons at the on-state that vigorously screen electron–electron interactions, reducing the band gap.^36,37 These screening mechanisms collectively justify using the GGA-PBE framework for accurate and computationally efficient modelling of nanoscale FET devices.

In the BL α-MoTe₂, the weak van der Waals forces of inter-planar coupling interactions are considered using the empirical correction based on Grimme DFT-D2.³⁸ The spin–orbit interaction is not taken into consideration because the interaction of spin–orbit coupling results in a minimal modulation of the electronic band structure of the pristine ML/BL α-MoTe₂³⁹ and is found to be closely consistent with the earlier reported study on few-layered α-MoTe₂-based FETs.⁴⁰ The device is simulated using a density-mesh cutoff of 125 Hartree and an electronic temperature of 300 K. A dense Monkhorst–Pack k-point mesh of 11 × 1 × 1 for the channel and 33 × 1 × 153 for the electrode region is sampled within the Brillouin zone. The atomic compensation charge approach is used to adjust the doping distribution.³¹ Solving the Poisson equations in the NEGF framework self-consistently estimates the transport phenomenon in the ML/BL α-MoTe₂ MOSFET.⁴¹

The primary kinetic equation that describes the non-equilibrium transport mechanism and the interaction within the electrodes and the central semiconductor channel in a MOSFET device is defined by the retarded Green's function G(E), given as:⁴²

	(1)

In the above equation, G(E) denotes the retarded Green's function, E signifies the injected energy; I is the identity matrix, H indicates the Hamiltonian of a single-electron within the channel, and Σ_S, Σ_D corresponds to the self-energy matrix terms for the source and drain electrodes, respectively. The matrix Σ_S, Σ_D captures the interaction of the semi-infinite source and drain electrodes with the scattering region (channel) of the finite device. Including self-energy terms ensures open boundary conditions, allowing electrons to enter and exit the device under applied bias. A transmission matrix T(E) is determined from the Green's function as:⁴³

T(E) = Trace[ASΓD] = Trace[ADΓS]	(2)

where A_S = GΓ_SG⁺, and A_D = GΓ_DG⁺ represent the spectral function of the source and drain electrodes, respectively. The Γ_S and Γ_D are the broadening matrices associated with the source and drain electrodes.

The output I_D (drain current) for a given V_g (gate-voltage) and V_b (bias-voltage) can be calculated by the Landauer–Büttiker formula, defined as:⁴⁴

	(3)

In eqn (3), the quantities h, e, k_B, T, and T(E) correspond to the Planck's constant, electronic charge, Boltzmann's constant, lattice temperature, and transmission function evaluated at energy E, respectively. f_S and f_D are the quantities characterizing the Fermi–Dirac distribution function of the source and drain electrodes having the corresponding chemical potentials μ_S and μ_D.

3. Results and discussion

3.1. Intrinsic properties of the pristine ML and BL α-MoTe₂

Although 2D materials show promise for next-generation electronics, not all are suitable as channel materials for FETs.⁴⁵ Evaluating their intrinsic properties is crucial to determining their potential for transistor application. In particular, the symmetrical atomic-scale structural and dynamic stability of 2D materials are critical for assessing their suitability as channel materials in FETs.⁴⁶ The bulk α-MoTe₂ is a semiconductor featuring an indirect band gap of approximately 1.0 eV. It consists of hexagonal layers of Mo-atoms sandwiched between two hexagonal planes of Te-atoms, exhibiting trigonal prismatic coordination. These Te–Mo–Te units, referred to as monolayers, are weakly held together by van der Waals forces and stacked in 2H-symmetry. The geometry of the pristine ML and BL α-MoTe₂ is optimized, as provided in Fig. 1(a). We considered the BL of α-MoTe₂ in AB-stacking, which is the most energetically favorable among various stacking arrangements and reflects the natural stacking sequence observed in bulk 2H-MoTe₂ as displayed in Fig. 2(b). Phonon dispersion spectra for the ML and BL α-MoTe₂ were calculated using the finite displacement method within the VASP-Phonopy interface.⁴⁷ Fully relaxed structures were used to generate 4 × 4 × 1 supercells, and forces from displaced configurations were obtained via static VASP calculations. The phonon dispersion spectra were then computed using Phonopy to assess dynamical stability.⁴⁸ The dynamical stability of the ML and BL α-MoTe₂ has been verified through phonon dispersion spectra calculations at 300 K, as shown in Fig. 2(c) and (d), which reveal the absence of imaginary vibration modes.

The bandgap (E_g) plays a critical role in the performance of 2D material-based devices.⁴⁹ It strongly influences both the off-state current (I_off) and the on/off current ratio (I_on/I_off) of the transistors. The I_off and I_on/I_off both depend exponentially on the E_g. The I_off follows the relation , while the I_on/I_off is given by . In both expressions, the parameter m depends on the transistor configuration and its factor ≥2, k_B is the Boltzmann constant, and T is the temperature. Ensuring the proper functioning of a logic-FET requires the bandgap of the channel material to be at least 0.4 eV for a sufficiently high I_on/I_off and effective switching speed.⁵⁰ The calculated band gap of the pristine ML α-MoTe₂ is 1.08 eV, as shown in Fig. 3(a), with both the valence band maximum (VBM) and conduction band minimum (CBM) located at the K-point, confirming its direct band gap nature. Direct band gap materials enable efficient inter-band transitions without requiring phonon assistance, thereby minimizing scattering and enhancing carrier transport and mobility. Quantum confinement effects significantly alter the electronic band structure of the BL α-MoTe₂ compared to that of the ML α-MoTe₂. The calculated band gap of the BL α-MoTe₂ is 0.88 eV, as shown in Fig. 3(b). Unlike the ML counterpart, BL α-MoTe₂ exhibits an indirect band gap, with the VBM at the Γ-point and the CBM at the Q-point. Indirect band gap materials enable efficient inter-band transitions, which can lead to increased scattering and lower carrier mobility. Therefore, the ML and BL α-MoTe₂ possess an optimal electronic band gap, rendering them promising as channel materials for FETs. Our computed band gap values without spin–orbit coupling (SOC) agree with experimental results. For instance, Ruppert et al.⁵¹ and Lezama et al.⁵² reported an experimental band gap of approximately 1.10 eV for monolayer α-MoTe₂ (direct K → K) and a reduced indirect band gap (Γ → Q) in the range of 0.85–0.95 eV for bilayer α-MoTe₂. Thus, our DFT results reproduce the direct-to-indirect band gap crossover and align well with available experimental data, validating the reliability of our computational framework.

In solids, the effective mass (m*) is a quantity used to simplify the analysis of electronic band structures by approximating the behaviour of a free particle possessing the same mass. The effective mass of electrons and holes is a key parameter in the channel material governing charge carrier mobility and the transport properties in FET devices.⁵³ We computed the carrier effective masses along the transport direction at the K, Γ, and the Q-valley of the conduction band minimum (CBM) and valence band maximum (VBM) of the ML and BL α-MoTe₂. The effective mass is calculated using the standard parabolic band approximation, expressed as: , where ℏ is the reduced Planck constant, E is the energy, and k is the wave vector. The calculated values of and are reported in Table 1. The notable difference in hole effective masses between monolayer (–0.688 m₀) and bilayer (–2.894 m₀) α-MoTe₂ arises from interlayer coupling effects that modify the valence band structure, as shown in Fig. 3. In the monolayer, strong in-plane Mo-d and Te-p orbital interactions yield a highly curved valence band and lower effective mass, while in the bilayer, interlayer Te-Te interactions flatten the band through hybridization, resulting in a much higher effective mass.

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The carrier mobility μ is related to the effective mass (m*), expressed as , where e is the elementary charge (e = 1.602 × 10⁻¹⁹ C), and τ is the scattering time. It is evident from the expression of μ that large m* along the transport directions will reduce carrier mobility, thereby hindering the conduction current.

3.2. Transfer IV-characteristics of the ML and BL α-MoTe₂ MOSFET

The transfer IV-characteristics are essential in quantum transport simulations for evaluating and analysing the most relevant electrical characteristics of FET device models, including I_on, I_off, I_on/I_off, SS, transconductance (g_m), and drain-induced barrier lowering (DIBL). The transfer IV-characteristics of the n- and p-type ML α-MoTe₂ MOSFET are calculated for HP and LP application, as shown in Fig. 4. To accurately capture the subthreshold region of the 0.34-nm L_g n- and p-type ML α-MoTe₂ device under varying L_UL, the gate-to-source voltage (V_gs) is swept from −2 V to 0 V for the n-type and from 0 V to 2 V for the p-type. A low I_off is a key performance indicator, suppressing leakage current and reducing static power dissipation. The I_off refers to the current flowing when the V_gs is zero and the V_ds is set to the supply voltage V_dd. The I_off and the corresponding V_g (off) are extracted from the transfer IV-characteristics in line with ITRS-2013 projections for the 2028 technology horizon. The benchmark for I_off is set at 0.01 μA μm⁻¹ for high-performance (HP) devices and 10⁻⁴ μA μm⁻¹ for low-power (LP) devices.

We also simulated the 0.34-nm L_g n- and p-type BL α-MoTe₂ MOSFET device and calculated the transfer IV-characteristics with varying L_UL as depicted in Fig. 5. Due to the quantum confinement, tunable indirect band gap, and degraded gate-control, the behaviour of the transfer IV-characteristics of the BL α-MoTe₂ n and p-type FET significantly differ from that of the ML. In terms of the ITRS-2013 standard projected for 2028 technology horizons, our n- and p-type BL α-MoTe₂ transistors failed to meet the standard requirements.

Based on the transfer IV-characteristics analysis, we evaluated the performance limits of the n- and p-type ML α-MoTe₂ FETs featuring the 0.34 nm gate-length. The performance is assessed by calculating the key FOMs, including I_on, SS, τ, and PDP, in line with the projected performance standards for 2028 horizons according to the ITRS-2013.

3.3. The FOMs of the ML α-MoTe₂ MOSFET

It is well-recognized that the doping concentration of the source and drain electrodes plays an integral role in determining the performance of FETs.^54,55 Considering the tunable bandgap of the α-MoTe₂ and the electrostatic influence of the underlap region, it is imperative to optimize the doping concentration to achieve the desired device characteristics at a specific V_g. We analyzed the transfer IV-characteristics of the n- and p-type ML and BL α-MoTe₂ FETs under doping concentrations ranging from 1 × 10¹² to 1 × 10¹⁴ cm⁻², with a V_dd = 0.54 V, as shown in Fig. 6(a). We determined the optimal doping level of 2 × 10¹³ cm⁻² for the n-type ML α-MoTe₂ FETs.

The I_on is directly measured from the transfer IV-characteristics with minimal uncertainty, refining it to be the more precise and reliable parameter for evaluating the performance of 2D FETs. The I_on is the source-to-drain current measured at the on-state voltage, V_on = V_dd ± V_off, where V_dd expresses the supply-voltage equal to the V_b (bias-voltage), and V_off is the off-state voltage corresponding to I_ds = I_off. The ‘+’ sign applies to the n-type devices, while the ‘−’ sign applies to the p-type devices. The calculated I_on for the n- and p-type ML α-MoTe₂ FETs for HP and LP applications with different L_UL are reported in Tables 2 and 3. According to the ITRS standard extended to the 0.34-nm L_g device, the value of I_on is 326 μA μm⁻¹ at V_dd = 0.54 V for the HP n- and p-type devices and 57 μA μm⁻¹ for LP device applications. Our n-type ML α-MoTe₂ FETs meet the ITRS standards, achieving an I_on of 396 μA μm⁻¹ for HP and 183 μA μm⁻¹ for LP applications, as depicted in Fig. 6(b) and (c).

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The gate-control is critical for transistor performance, and enhancing this control is a key strategy to mitigate SCEs. It is typically assessed by the SS, a key parameter that characterizes the switching efficiency of a transistor. SS is defined as the gate voltage change needed to increase the drain current by one order of magnitude in the subthreshold region, expressed as . A smaller SS value signifies a strong gate control, reflecting enhanced performance and efficiency. In ideal transistors, the subthreshold swing is theoretically limited to 60 mV decade⁻¹ at room temperature (300 K). This limit is a consequence of the inherent thermionic emission process of charge carriers, which is governed by the Boltzmann distribution.⁵⁶ Fig. 6(d) shows the impact of L_UL on SS for the 0.34-nm L_g n-type ML α-MoTe₂ FETs. The minimum value of the SS for the HP n-type ML α-MoTe₂ FETs is 151 mV dec⁻¹ achieved at L_UL = 2 nm, and for LP is 88 mV dec⁻¹ at L_UL = 3 nm. These results highlight the importance of L_UL in optimizing gate controllability for the 0.34-nm L_g n-type ML α-MoTe₂ FETs. These minimum SS values indicate improved gate-control and switching efficiency, with enhanced performance for HP and LP devices at their optimal L_UL values.

Since the ITRS standard is only a reference, we also compare our n-type device performance in terms of I_on and SS with other ab initio simulation results for the most studied 2D material-based transistors with L_g ≤ 1 nm, as illustrated in Fig. 7. The scattered data in the figure shows that the I_on of our n-type ML α-MoTe₂ FETs is comparable to that of the widely studied ML MoS₂ FETs at the sub-1 nm L_g. The SS values for our device demonstrate promising switching characteristics, though still slightly higher than those observed in the MoS₂ FETs, suggesting potential for further optimization in switching efficiency.

To further explore the gate control mechanism, we analyze the projected local device density of states (PLDOS) of the ML n-type transistor with L_UL of 2-nm under both off- and on-state V_g conditions. The PLDOS plots illustrate the spatially resolved electronic states along the transport direction (z-axis) of the ML α-MoTe₂ FET, as shown in Fig. 8(a) and (b). The energy-resolved local density of states (LDOS) is color-coded, where black indicates low density and pink indicates high density of electronic states. To estimate the potential barrier height (Φ_B) in both the off-state and on-state from the PLDOS, we analyze the conduction band profile above the Fermi level (yellow contour line) in the channel region, particularly where the band reaches its maximum along the transport direction (z-axis).

The conduction band edge in the off-state exhibits a pronounced energy barrier between the source and drain, effectively suppressing the carrier injection across the channel. This barrier potential shows a direct consequence of the gate-induced electrostatics. It creates a difference in the chemical potential (ε_L) of the source, i.e., the left electrode and the available conduction states in the channel, resulting in minimal carrier transmission and, thus, a low I_off. In the off-state, the conduction band peaks at approximately 0.73 eV above the ε_L, resulting in an estimated barrier height of 0.73 eV. The applied V_dd of 0.54 V introduces a potential drop across the channel, seen as an energy difference between ε_L and ε_R. The extent of the barrier modulation between the off- and on-states is a critical indicator of gate control, essential for achieving a high I_on/I_off current ratio and optimal subthreshold performance in ultra-scaled FETs.

In contrast, the on-state PLDOS plot shows a substantial barrier lowering, with the conduction band aligning closer to ε_L and ε_R. In the on-state, the conduction band is significantly lowered, with the peak positioned approximately 0.51 eV above ε_L, resulting in an estimated barrier height of 0.51 eV. This electrostatic modulation flattens the potential barrier across the channel, enabling efficient carrier transport and resulting in a significantly higher I_on. These values of Φ_B at the off and on-state show a strong gate-induced modulation (∼0.22 eV barrier lowering), indicative of excellent electrostatic control in the ultra-scaled 0.34-nm ML MoTe₂ FET.

In addition to I_on and SS, we investigated two other key performance indicators: intrinsic delay-time (τ) and power dissipation (PDP). In the context of FETs, the τ represents the time it takes for a transistor to switch from one state (on or off) to another, typically from the off-state to the on-state. Shorter τ indicates faster switching speeds, crucial for high-speed electronics such as processors and communication devices. The τ is influenced by factors like the capacitance of the gate (C_g), I_on, and V_dd, expressed as: . The C_t = 3C_g, and C_g is expressed as; , where Q_ch shows the total charge accumulated in the central channel region under V_dd of 0.54 V, and W is the width of the device. The calculated τ for the 0.34-nm L_g n-type ML α-MoTe₂ FETs with optimized L_UL = 2 nm is 0.334 ps for HP and 1.075 ps for LP. These values satisfy the ITRS standard, as reported in Tables 2 and 3.

PDP is a critical FOM for assessing speed and power consumption trade-offs. PDP is determined as the product of the power consumed (P) and the τ during the one switching operation and is formulated as PDP = τP = C_tV²_dd. Since the V_dd is 0.54 V, the PDP is primarily influenced by the C_t. A lower PDP is desired because it indicates a transistor that can switch faster while consuming less power. The calculated PDP numerical values for our n-type ML α-MoTe₂ FETs with optimized L_UL = 2 nm are 0.071 fJ μm⁻¹ for HP and 0.060 fJ μm⁻¹ for LP applications, meet the ITRS standard and are reported in Tables 2 and 3.

4. Conclusion

In conclusion, this research utilized the DFT + NEGF formalism for quantum transport simulation to evaluate the performance limit of the n- and p-type sub-1 nm gate-length ML and BL α-MoTe₂ FETs for HP and LP applications. The FETs are simulated under an ultra-low bias voltage of 0.54 V. The n-type ML α-MoTe₂ FETs meet the requirements of the ITRS standard for HP and LP devices in terms of I_on [396 μA μm⁻¹ (HP) and 183 μA μm⁻¹ (LP)], τ[0.334 ps (HP) and 1.075 ps (LP)] and PDP [0.071 fJ μm⁻¹ (HP) and 0.060 fJ μm⁻¹ (LP)]. The p-type ML and the n- and p-type BL α-MoTe₂ transistors fail to meet the ITRS requirements for HP and LP devices because of the high effective mass of holes. The minimum SS for the HP n-type ML α-MoTe₂ FETs is 151 mV dec⁻¹, and that for the LP is 88 mV dec⁻¹. The findings presented here represent a significant step toward developing the n-type sub-1 nm gate-length FETs based on the ML α-MoTe₂.

Author contributions

Mudasser Husain: conceptualization, methodology, software, investigation, data curation, formal analysis, writing – original draft, writing – review and editing. Younas Ahmed: visualization. Xingyue Yang: methodology, validation. Shibo Fang: formal analysis, conceptualization. Zongmeng Yang: data curation, validation. Jichao Dong: visualization. Linqiang Xu: methodology, visualization. Nasir Rahman: formal analysis. Jing Lu: conceptualization, writing – review and editing, funding acquisition, project administration, resources, supervision, validation, visualization.

Conflicts of interest

The authors declare no competing financial interest.

Data availability

The data supporting the findings of this study are available from the corresponding author upon reasonable request.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (No. 12274002 and 91964101), the Ministry of Science and Technology of China (No. 2022YFA1203904), the Fundamental Research Funds for the Central Universities, the High-performance Computing Platform of Peking University and the MatCloud + high throughput materials simulation engine. S. Fang is supported by the National Research Foundation, Singapore, under its Frontier Competitive Research Programme (NRF-F-CRP-2024-0001). We thank Y. S. A. for insightful discussions.

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