Highly-efficient and scalable TrioN (3N0C) synaptic cell for analog process-in-memory

Abstract

The development of non-volatile memory (NVM)-based cross-point arrays has paved the way for the realization of neuromorphic architectures toward analog process-in-memory (aPIM). However, the inherent non-ideal characteristics of NVM devices such as asymmetry necessitate capacitor-based synaptic cells. We introduce a capacitorless 3-NMOS 0-capacitor (TrioN, 3N0C) cross-point device, a novel synaptic cell leveraging amorphous indium gallium zinc oxide (a-IGZO), and a promising oxide semiconductor with low off-current. Using only NMOS transistors, TrioN enables high-density arrays with a simplified fabrication process without the need for PMOS or external capacitors. It exhibits excellent switching characteristics, including perfect symmetry, a high on/off ratio, and ultra-fast 10 ns switching. Fabricated hardware demonstrates precise selective updates, supporting 2-cycle updates for improved speed and energy efficiency over conventional 4-cycle methods. Neural network simulations using stochastic gradient descent (SGD) and Tiki-Taka algorithm version 1 (TTv1) on a multi-layer perceptron (MLP) for the MNIST dataset achieve high accuracy of 96.89% and 97.19%, respectively. These results highlight TrioN's potential as a compact, energy-efficient, and scalable solution for neuromorphic computing.

Graphical abstract: Highly-efficient and scalable TrioN (3N0C) synaptic cell for analog process-in-memory

Supplementary files

Article information

Article type
Communication
Submitted
22 Feb 2025
Accepted
03 Jun 2025
First published
25 Jun 2025
This article is Open Access
Creative Commons BY-NC license

Mater. Horiz., 2025, Advance Article

Highly-efficient and scalable TrioN (3N0C) synaptic cell for analog process-in-memory

J. Choi, B. Lee, J. Byun, H. Kim, S. Kim, J. Lee, H. Kwak, J. Son and S. Kim, Mater. Horiz., 2025, Advance Article , DOI: 10.1039/D5MH00324E

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